MC68HC16R1/916R1
USER’S MANUAL
MOTOROLA
v
(Continued)
Title
Paragraph
Page
TABLE OF CONTENTS
4.14.3
4.14.4
4.14.4.1
4.14.4.2
4.14.4.3
4.14.4.4
4.14.4.5
4.14.4.6
4.15
4.16
Opcode Tracking and Breakpoints ..................................................4-42
Background Debug Mode ................................................................4-42
Enabling BDM .........................................................................4-42
BDM Sources ..........................................................................4-42
Entering BDM ..........................................................................4-43
BDM Commands .....................................................................4-43
Returning from BDM ...............................................................4-44
BDM Serial Interface ...............................................................4-44
Recommended BDM Connection ............................................................4-45
Digital Signal Processing .........................................................................4-46
SECTION 5
SINGLE-CHIP INTEGRATION MODULE 2
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.5
5.5.1
5.5.1.1
5.5.1.2
5.5.1.3
5.5.1.4
General ......................................................................................................5-1
System Configuration ................................................................................5-2
Module Mapping ................................................................................5-3
Interrupt Arbitration ............................................................................5-3
Single-Chip Operation Support .........................................................5-3
Show Internal Cycles .........................................................................5-4
Register Access ................................................................................5-4
Freeze Operation ..............................................................................5-4
System Clock ............................................................................................5-4
Clock Sources ...................................................................................5-5
Clock Synthesizer Operation .............................................................5-6
External Bus Clock ..........................................................................5-14
Low-Power Operation ......................................................................5-14
System Protection ...................................................................................5-16
Reset Status ....................................................................................5-16
Bus Monitor .....................................................................................5-16
Halt Monitor .....................................................................................5-17
Spurious Interrupt Monitor ...............................................................5-17
Software Watchdog .........................................................................5-17
Periodic Interrupt Timer ...................................................................5-20
Interrupt Priority and Vectoring ........................................................5-21
Low-Power STOP Operation ...........................................................5-21
External Bus Interface .............................................................................5-22
Bus Control Signals .........................................................................5-24
Address Bus ............................................................................5-24
Address Strobe .......................................................................5-24
Data Bus .................................................................................5-24
Data Strobe .............................................................................5-24