MOTOROLA
5-72
SINGLE-CHIP INTEGRATION MODULE 2
MC68HC16R1/916R1
USER’S MANUAL
Port E pin assignment register (PEPAR) bits control the function of each port E pin.
Any bit set to one defines the corresponding pin to be a bus control signal, with the
function shown in
Table 5-28
. Any bit cleared to zero defines the corresponding pin to
be an I/O pin, controlled by PORTE and DDRE.
BERR and DATA8 control the state of this register following reset. If BERR and/or
DATA8 are low during reset, this register is set to $00, defining all port E pins as I/O
pins. If BERR and DATA8 are both high during reset, the register is set to $FF, which
defines all port E pins as bus control signals.
5.10.3 Port F
Port F consists of eight I/O pins, a data register, a data direction register, a pin assign-
ment register, an edge-detect flag register, an edge-detect interrupt vector register, an
edge-detect interrupt level register, and associated control logic.
Figure 5-23
is a
block diagram of port F pins, registers, and control logic.
Port F pins can be configured as interrupt request inputs, edge-detect input/outputs,
or discrete input/outputs. When port F pins are configured for edge detection, and a
priority level is specified by writing a value to the port F edge-detect interrupt level
register (PFLVR), port F control logic generates an interrupt request when the
specified edge is detected. Interrupt vector assignment is made by writing a value to
the port F edge-detect interrupt vector register (PFIVR). The edge-detect interrupt has
the lowest arbitration priority in the SCIM2.
A write to the port F data register (PORTF) is stored in the internal data latch, and if
any port F pin is configured as an output, the value stored for that bit is driven on the
pin. A read of PORTF returns the value on a pin only if the pin is configured as a dis-
crete input. Otherwise, the value read is the value stored in the data register. PORTF
is a single register that can be accessed in two locations (PORTF1, PORTF0). It can
be read or written at any time, including when the MCU is in emulator mode.
Port F data direction register (DDRF) bits control the direction of port F pin drivers
when the pins are configured for I/O. Setting any bit in this register configures the
corresponding pin as an output. Clearing any bit in this register configures the
corresponding pin as an input.
Table 5-28 Port E Pin Assignments
PEPAR Bit
PEPA7
PEPA6
PEPA5
PEPA4
PEPA2
PEPA1
PEPA0
Port E Signal
PE7
PE6
PE5
PE4
PE2
PE1
PE0
Bus Control Signal
SIZ1
SIZ0
AS
DS
AVEC
DSACK1
DSACK0