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| 型號： | MC68HC912BL16VFU8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 93/128頁 |
| 文件大?。?/td> | 3326K |
| 代理商： | MC68HC912BL16VFU8 |
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MC68HC912BL16TS/D
67
11 Pulse-Width Modulator
The pulse-width modulator (PWM) subsystem provides four independent 8-bit PWM waveforms or two
16-bit PWM waveforms or a combination of one 16-bit and two 8-bit PWM waveforms. Each waveform
channel has a programmable period and a programmable duty-cycle as well as a dedicated counter. A
flexible clock select scheme allows four different clock sources to be used with the counters. Each of
the modulators can create independent, continuous waveforms with software-selectable duty rates from
0 percent to 100 percent. The PWM outputs can be programmed as left-aligned outputs or center-
aligned outputs.
The period and duty registers are double buffered so that if they change while the channel is enabled,
the change will not take effect until the counter rolls over or the channel is disabled. If the channel is not
enabled, then writes to the period and/or duty register will go directly to the latches as well as the buffer,
thus ensuring that the PWM output will always be either the old waveform or the new waveform, not
some variation in between.
For Center Aligned mode two additional initialization operations occur: the PWM counter is reset to $00
and a decision for the PWM output value takes place. In this way the output of the PWM will always be;
the old waveform, or the new waveform and not some variation of the two.
A change in duty or period can be forced into immediate effect by writing the new value to the duty and/
or period registers and then writing to the counter. This causes the counter to reset and the new duty
and/or period values to be latched. In addition, since the counter is readable it is possible to know where
the count is with respect to the duty value and software can be used to make adjustments by turning
the enable bit off and on.
The four PWM channel outputs share general-purpose port P pins. Enabling PWM pins takes prece-
dence over the general-purpose port. When PWM are not in use, the port pins may be used for discrete
input/output.
Figure 17 Block Diagram of PWM Left-Aligned Output Channel
GATE
PWCNTx
8-BIT COMPARE =
PWDTYx
8-BIT COMPARE =
PWPERx
UP/DOWN
FROM PORT P
DATA REGISTER
TO PIN
DRIVER
PPOLx
CLOCK SOURCE
(ECLK)
(CLOCK EDGE SYNC)
RESET
CENTR = 0
MUX
S
R
Q
PWPER
PWDTY
PWENx
PPOL = 0
PPOL = 1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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