參數(shù)資料
型號： MC68HC912BL16VFU8
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 114/128頁
文件大小： 3326K
代理商： MC68HC912BL16VFU8
MC68HC912BL16
86
MC68HC912BL16TS/D
0 = Normal operation
1 = The 16-bit pulse accumulator counter is divided into two 8-bit halves and the prescaler is by-
passed. The clock drives both halves directly.
PORTT can be read anytime. When configured as an input, a read will return the pin level. When con-
figured as output, a read will return the latched output data.
NOTE
Writes do not change pin state when the pin is configured for timer output. The minimum pulse width
for pulse accumulator input should always be greater than two module clocks due to input synchronizer
circuitry. The minimum pulse width for the input capture should always be greater than the width of two
module clocks due to input synchronizer circuitry.
Port T[6] is not bonded to any pin in MC68HC912BL16.
Read or write anytime.
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output
The timer forces the I/O state to be an output for each timer port pin associated with an enabled output
compare. In these cases the data direction bits will not be changed but have no affect on the direction
of these pins. The DDRT will revert to controlling the I/O direction of a pin when the associated timer
output compare is disabled. Input captures do not override the DDRT settings.
12.2 Timer Operation in Modes
STOP:
Timer is off since both PCLK and ECLK are stopped.
BDM:
Timer keeps running, unless TSBCK = 1
WAIT:
Counters keep running, unless TSWAI = 1
NORMAL: Timer keeps running, unless TEN = 0
TEN = 0:
All timer operations are stopped, registers may be accessed.
Gated pulse accumulator
÷64 clock is also disabled.
PAEN = 0: All pulse accumulator operations are stopped, registers may be accessed.
PORTT — Timer Port Data Register
$00AE
Bit 7
6
5
4
3
2
1
Bit 0
PT7
PT6
PT5
PT4
PT3
PT2
PT1
PT0
TIMER
I/OC7
I/OC6
I/OC5
I/OC4
I/OC3
I/OC2
I/OC1
I/OC0
PA
PAI
DDRT — Data Direction Register for Timer Port
$00AF
Bit 7
6
5
4
3
2
1
Bit 0
DDT7
DDT6
DDT5
DDT4
DDT3
DDT2
DDT1
DDT0
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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