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| 型號(hào)： | MC68HC912BL16VFU8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 24/128頁(yè) |
| 文件大小： | 3326K |
| 代理商： | MC68HC912BL16VFU8 |
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MC68HC912BL16
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MC68HC912BL16TS/D
3.3.3 Reset (RESET)
An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known start-
up state. It also acts as an open-drain output to indicate that an internal failure has been detected in
either the clock monitor or COP watchdog circuit. The MCU goes into reset asynchronously and comes
out of reset synchronously. This allows the part to reach a proper reset state even if the clocks have
failed, while allowing synchronized operation when starting out of reset.
It is possible to determine whether a reset was caused by an internal source or an external source. An
internal source drives the pin low for 16 cycles; eight cycles later the pin is sampled. If the pin has re-
turned high, either the COP watchdog vector or clock monitor vector will be taken. If the pin is still low,
the external reset is determined to be active and the reset vector is taken. Hold reset low for at least 32
cycles to assure that the reset vector is taken in the event that an internal COP watchdog time-out or
clock monitor fail occurs.
3.3.4 Maskable Interrupt Request (IRQ)
The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling
edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is al-
ways configured to level-sensitive triggering at reset. When the MCU is reset the IRQ function is
masked in the condition code register.
3.3.5 Nonmaskable Interrupt (XIRQ)
The XIRQ input provides a means of requesting a nonmaskable interrupt after reset initialization. During
reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU soft-
ware enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source
wired-OR network. This pin is always an input and can always be read. There is an active pull-up on
this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPE in
the PUCR register. XIRQ is often used as a power loss detect interrupt.
Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ must be configured for level-sen-
sitive operation if there is more than one source of IRQ interrupt), each source must drive the interrupt
input with an open-drain type of driver to avoid contention between outputs. There must also be an in-
terlock mechanism at each interrupt source so that the source holds the interrupt line low until the MCU
recognizes and acknowledges the interrupt request. If the interrupt line is held low, the MCU will recog-
nize another interrupt as soon as the interrupt mask bit in the MCU is cleared (normally upon return from
an interrupt).
3.3.6 Mode Select (SMODN, MODA, and MODB)
The state of these pins during reset determine the MCU operating mode. After reset, MODA and MODB
can be configured as instruction queue tracking signals IPIPE0 and IPIPE1. MODA and MODB have
active pulldowns during reset.
The SMODN pin can be used as BKGD or TAGHI after reset.
3.3.7 Single-Wire Background Mode Pin (BKGD)
The BKGD pin receives and transmits serial background debugging commands. A special self-timing
protocol is used. The BKGD pin has an active pull-up when configured as input; BKGD has no pull-up
control. Refer to 16 Development Support.
3.3.8 External Address and Data Buses (ADDR[15:0] and DATA[15:0])
External bus pins share function with general-purpose I/O ports A and B. In single-chip operating
modes, the pins can be used for I/O; in expanded modes, the pins are used for the external buses.
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