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| 型號(hào)： | MC68HC912BL16CFU8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 82/128頁(yè) |
| 文件大?。?/td> | 3326K |
| 代理商： | MC68HC912BL16CFU8 |
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MC68HC912BL16TS/D
57
9.5.3 Interrupts
PSEL is initialized in the HPRIO register with the value $F2, causing the external IRQ pin to have the
highest I-bit interrupt priority. The IRQ pin is configured for level-sensitive operation (for wired-OR sys-
tems). However, the interrupt mask bits in the CPU12 CCR are set to mask X and I related interrupt
requests.
9.5.4 Parallel I/O
If the MCU comes out of reset in an expanded mode, port A and port B are used for the multiplexed
address/data bus and port E pins are normally used to control the external bus (operation of port E pins
can be affected by the PEAR register). If the MCU comes out of reset in a single-chip mode, all ports
are configured as general-purpose high-impedance inputs. Port S, port T, port P, and port AD are all
configured as general-purpose inputs.
9.5.5 Central Processing Unit
After reset, the CPU fetches a vector from the appropriate address, then begins executing instructions.
The stack pointer and other CPU registers are indeterminate immediately after reset. The CCR X and
I interrupt mask bits are set to mask any interrupt requests. The S bit is also set to inhibit the STOP
instruction.
9.5.6 Memory
After reset, the internal register block is located at $0000–$01FF, the register-following space is at
$0200–$03FF, and RAM is at $0800–$09FF. EEPROM is located at $0E00–$0FFF. Flash EEPROM is
located at $C000–$FFFF in single-chip modes and at $4000–$7FFF (but disabled) in expanded modes.
9.5.7 Other Resources
The timer, serial communications interface (SCI), serial peripheral interface (SPI), pulse-width modula-
tor (PWM), and analog-to-digital converter (ATD) are off after reset.
9.6 Register Stacking
Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared.
When an interrupt service request is recognized, the CPU responds at the completion of the instruction
being executed. Interrupt latency varies according to the number of cycles required to complete the in-
struction. Some of the longer instructions can be interrupted and will resume normally after servicing
the interrupt.
When the CPU begins to service an interrupt, the instruction queue is cleared, the return address is cal-
culated, and then it and the contents of the CPU registers are stacked as shown in Table 18.
After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt service request is pending) is set
to prevent other interrupts from disrupting the interrupt service routine. The interrupt vector for the high-
est priority source that was pending at the beginning of the interrupt sequence is fetched, and execution
continues at the referenced location. At the end of the interrupt service routine, an RTI instruction re-
stores the content of all registers from information on the stack, and normal program execution re-
sumes. If another interrupt is pending at the end of an interrupt service routine, the register unstacking
and restacking is bypassed and the vector of the pending interrupt is fetched.
Table 18 Stacking Order on Entry to Interrupts
Memory Location
CPU Registers
SP – 2
RTNH : RTNL
SP – 4
YH : YL
SP – 6
XH : XL
SP – 8
B : A
SP – 9
CCR
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