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| 型號(hào)： | MC68HC912BL16CFU8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 28/128頁(yè) |
| 文件大?。?/td> | 3326K |
| 代理商： | MC68HC912BL16CFU8 |
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MC68HC912BL16TS/D
123
Single full-feature breakpoint which will cause the part to enter background debug mode (BDM)
Dual address-only breakpoints, each of which will cause the part to enter BDM
Breakpoints will not occur when BDM is active.
15.3.1.1 SWI Dual Address Mode
In this mode, dual address-only breakpoints can be set, each of which cause a software interrupt. This
is the only breakpoint mode which can force the CPU to execute a SWI. Program fetch tagging is the
default in this mode; data breakpoints are not possible. In the dual mode each address breakpoint is
affected by the respective BKALE bit. The BKxRW, BKxRWE, BKMBH and BKMBL bits are ignored. In
dual address mode the BKDBE becomes an enable for the second address breakpoint.
15.3.1.2 BDM Full Breakpoint Mode
This is a single full-featured breakpoint which causes the part to enter background debug mode.
BK1ALE, BK1RW, and BK1RWE have no meaning in full breakpoint mode.
BKDBE enables data compare but has no meaning if BKPM=1. BKMBH and BKMBL allow masking of
high and low byte compares but has no meaning if BKPM=1. BK0ALE enables compare of low address
byte.
Breakpoints are not allowed if the BDM mode is already active. Active mode means the CPU is
executing out of the BDM ROM.
BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. This is
important because even if the ENABLE bit in the BDM is negated the CPU actually does execute
the BDM ROM code. It checks the ENABLE and returns if not set. If the BDM is not serviced by
the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow.
There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled.
15.3.1.3 BDM Dual Address Mode
Dual address-only breakpoints, each of which cause the part to enter background debug mode. In the
dual mode each address breakpoint is affected by the BKPM bit, the BKxALE bits, and the BKxRW and
BKxRWE bits. In dual address mode the BKDBE becomes an enable for the second address break-
point. The BKMBH and BKMBL bits will have no effect when in a dual address mode. BDM mode may
be entered by a breakpoint only if an internal signal from the BDM indicates background debug mode
is enabled. If BKPM = 1 then BKxRW, BKxRWE, BKMBH and BKMBL have no meaning.
Breakpoints are not allowed if the BDM mode is already active. Active mode means the CPU is
executing out of the BDM ROM.
BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. This is
important because even if the ENABLE bit in the BDM is negated the CPU actually does execute
the BDM ROM code. It checks the ENABLE and returns if not set. If the BDM is not serviced by
the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow.
There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled.
15.3.2 Registers
Breakpoint operation consists of comparing data in the breakpoint address registers (BRKAH/BRKAL)
to the address bus and comparing data in the breakpoint data registers (BRKDH/BRKDL) to the data
bus. The breakpoint data registers can also be compared to the address bus. The scope of comparison
can be expanded by ignoring the least significant byte of address or data matches.
The scope of comparison can be limited to program data only by setting the BKPM bit in breakpoint con-
trol register 0.
To trace program flow, setting the BKPM bit causes address comparison of program data only. Control
bits are also available that allow checking read/write matches.
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