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參數(shù)資料
| 型號： | MC68HC912BL16CFU8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 17/128頁 |
| 文件大?。?/td> | 3326K |
| 代理商： | MC68HC912BL16CFU8 |
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MC68HC912BL16TS/D
113
15 Development Support
Development support involves complex interactions between MC68HC912BL16 resources and exter-
nal development systems. The following section concerns instruction queue and queue tracking sig-
nals, background debug mode, breakpoints, and instruction tagging.
15.1 Instruction Queue
It is possible to monitor CPU activity on a cycle-by-cycle basis for debugging.The CPU12 instruction
queue provides at least three bytes of program information to the CPU when instruction execution be-
gins. The CPU12 always completely finishes executing an instruction before beginning to execute the
next instruction. Status signals IPIPE[1:0] provide information about data movement in the queue and
indicate when the CPU begins to execute instructions. Information available on the IPIPE[1:0] pins is
time multiplexed. External circuitry can latch data movement information on rising edges of the E-clock
signal; execution start information can be latched on falling edges. Table 37 shows the meaning of data
on the pins.
Program information is fetched a few cycles before it is used by the CPU. In order to monitor cycle-by-
cycle CPU activity, it is necessary to externally reconstruct what is happening in the instruction queue.
Internally the MCU only needs to buffer the data from program fetches. For system debug it is necessary
to keep the data and its associated address in the reconstructed instruction queue. The raw signals re-
quired for reconstruction of the queue are ADDR, DATA, R/W, ECLK, and status signals IPIPE[1:0].
The instruction queue consists of two 16-bit queue stages and a holding latch on the input of the first
stage. To advance the queue means to move the word in the first stage to the second stage and move
the word from either the holding latch or the data bus input buffer into the first stage. To start even (or
odd) instruction means to execute the opcode in the high-order (or low-order) byte of the second stage
of the instruction queue.
15.2 Background Debug Mode
Background debug mode (BDM) is used for system development, in-circuit testing, field testing, and
programming. BDM is implemented in on-chip hardware and provides a full set of debug options.
Table 37 IPIPE Decoding
Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock1
NOTES:
1. Refers to data that was on the bus at the previous E falling edge.
IPIPE[1:0]
Mnemonic
Meaning
0:0
—
No Movement
0:1
LAT
Latch Data From Bus
1:0
ALD
Advance Queue and Load From Bus
1:1
ALL
Advance Queue and Load From Latch
Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock2
2. Refers to bus cycle starting at this E falling edge.
IPIPE[1:0]
Mnemonic
Meaning
0:0
—
No Start
0:1
INT
Start Interrupt Sequence
1:0
SEV
Start Even Instruction
1:1
SOD
Start Odd Instruction
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For More Information On This Product,
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