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參數(shù)資料
| 型號： | MC68HC912BL16CFU8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 20/128頁 |
| 文件大?。?/td> | 3326K |
| 代理商： | MC68HC912BL16CFU8 |
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MC68HC912BL16
116
MC68HC912BL16TS/D
on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but
the target MC68HC912BL16 finishes it. Since the target wants the host to receive a logic zero, it drives
the BKGD pin low for 13 E-clock cycles, then briefly drives it high to speed up the rising edge. The host
samples the bit level about ten cycles after starting the bit time.
15.2.2 Enabling BDM Firmware Commands
BDM is available in all operating modes, but must be made active before firmware commands can be
executed. BDM is enabled by setting the ENBDM bit in the BDM STATUS register via the single wire
interface (using a hardware command; WRITE_BD_BYTE at $FF01). BDM must then be activated to
map BDM registers and ROM to addresses $FF00 to $FFFF and to put the MCU in active background
mode.
After the firmware is enabled, BDM can be activated by the hardware BACKGROUND command, by
the BDM tagging mechanism, or by the CPU BGND instruction. An attempt to activate BDM before firm-
ware has been enabled causes the MCU to resume normal instruction execution after a brief delay.
BDM becomes active at the next instruction boundary following execution of the BDM BACKGROUND
command, but tags activate BDM before a tagged instruction is executed.
In special single-chip mode, background operation is enabled and active immediately out of reset. This
active case replaces the M68HC11 boot function, and allows programming a system with blank mem-
ory.
While BDM is active, a set of BDM control registers are mapped to addresses $FF00 to $FF06. The
BDM control logic uses these registers which can be read anytime by BDM logic, not user programs.
Refer to 15.2.4 BDM Registers for detailed descriptions.
Some on-chip peripherals have a BDM control bit which allows suspending the peripheral function dur-
ing BDM. For example, if the timer control is enabled, the timer counter is stopped while in BDM. Once
normal program flow is continued, the timer counter is re-enabled to simulate real-time operations.
15.2.3 BDM Commands
All BDM command opcodes are eight bits long, and can be followed by an address and/or data, as in-
dicated by the instruction. These commands do not require the CPU to be in active BDM mode for ex-
ecution.
The host controller must wait 150 cycles for a non-intrusive BDM command to execute before another
command can be sent. This delay includes 128 cycles for the maximum delay for a dead cycle. For data
read commands, the host must insert this delay between sending the address and attempting to read
the data.
BDM logic retains control of the internal buses until a read or write is completed. If an operation can be
completed in a single cycle, it does not intrude on normal CPU operation. However, if an operation re-
quires multiple cycles, CPU clocks are frozen until the operation is complete.
There are two types of BDM commands: hardware and firmware. Hardware commands allow target
system memory to be read or written. Target system memory includes all memory that is accessible by
the CPU12 including on-chip RAM, EEPROM, on-chip I/O and control registers, and external memory
connected to the target HC12 MCU. Hardware commands are implemented in hardware logic and do
not require the HC12 MCU to be in BDM mode for execution. The control logic watches the CPU12 bus-
es to find a free bus cycle to execute the command so that the background access does not disturb the
running application programs. If a free cycle is not found within 128 E-clock cycles, the CPU12 is mo-
mentarily frozen so the control logic can steal a cycle. Refer to Table 38 for commands implemented in
BDM control logic.
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