參數資料
型號： MC68HC711D3MFN3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數： 91/157頁
文件大小： 2252K
代理商： MC68HC711D3MFN3
Central Processor Unit (CPU)
CPU Registers
MC68HC711D3 — Rev. 2
Data Sheet
MOTOROLA
Central Processor Unit (CPU)
39
3.2.5 Program Counter (PC)
The program counter, a 16-bit register, contains the address of the next instruction
to be executed. After reset, the program counter is initialized from one of six
possible vectors, depending on operating mode and the cause of reset.
3.2.6 Condition Code Register (CCR)
This 8-bit register contains:
Five condition code indicators (C, V, Z, N, and H)
Two interrupt masking bits (IRQ and XIRQ)
One stop disable bit (S)
In the M68HC11 CPU, condition codes are updated automatically by most
instructions. For example, load accumulator A (LDAA) and store accumulator A
(STAA) instructions automatically set or clear the N, Z, and V condition code flags.
Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange
instructions do not affect the condition codes. Refer to Table 3-2, which shows
what condition codes are affected by a particular instruction.
3.2.6.1 Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during
an arithmetic operation. The C bit also acts as an error flag for multiply and divide
operations. Shift and rotate instructions operate with and through the carry bit to
facilitate multiple-word shift operations.
3.2.6.2 Overflow (V)
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the
V bit is cleared.
3.2.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation operation
is 0. Otherwise, the Z bit is cleared. Compare instructions do an internal implied
subtraction and the condition codes, including Z, reflect the results of that
subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and no
other condition flags. For these operations, only = and
≠ conditions can be
determined.
Table 3-1. Reset Vector Comparison
Mode
POR or RESET Pin
Clock Monitor
COP Watchdog
Normal
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
Test or boot
$BFFE, $BFFF
$BFFC, $FFFD
$BFFA, $FFFB
相關PDF資料
PDF描述
MCC68HC711D3 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC
MC68HC711D3MP2 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP40
MC68HC711D3S 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP40
MC68HC711D3FN 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44
MC68HC711G5CFN 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC84
相關代理商/技術參數
參數描述
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