參數(shù)資料
型號： MC68HC711D3MFN3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 150/157頁
文件大?。?/td> 2252K
代理商： MC68HC711D3MFN3
Serial Peripheral Interface (SPI)
Data Sheet
MC68HC711D3 — Rev. 2
92
Serial Peripheral Interface (SPI)
MOTOROLA
transfer begins when the SCK line goes to its active level, which is the edge at the
beginning of the first SCK cycle. The transfer ends in a slave in which CPHA equals
one when SPIF is set. For a slave, after a byte transfer, SCK must be in inactive
state for at least 2 E-clock cycles before the next byte transfer begins.
7.7 SPI Registers
The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and
data storage functions. This sub-section provides a description of how these
registers are organized.
7.7.1 SPI Control Register
SPIE — Serial Peripheral Interrupt Enable Bit
0 = SPI interrupt disabled
1 = SPI interrupt enabled
SPE — Serial Peripheral System Enable Bit
0 = SPI off
1 = SPI on
DWOM — Port D Wired-OR Mode Bit
DWOM affects all six port D pins.
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select Bit
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being transferred, the SCK
pin of the master device has a steady state low value. When CPOL is set, SCK
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data
relationship between master and slave. The CPHA bit selects one of two
different clocking protocols. Refer to Figure 7-2 and 7.4 Clock Phase and
Address:
$0028
Bit 7
654321
Bit 0
Read:
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
Write:
Reset:
000001
U
U = Unaffected
Figure 7-3. SPI Control Register (SPCR)
相關(guān)PDF資料
PDF描述
MCC68HC711D3 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC
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