參數(shù)資料
型號： MC68HC711D3MFN3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 108/157頁
文件大小： 2252K
代理商： MC68HC711D3MFN3
Resets, Interrupts, and Low-Power Modes
Data Sheet
MC68HC711D3 — Rev. 2
54
Resets, Interrupts, and Low-Power Modes
MOTOROLA
CR1 and CR0 — COP Timer Rate Selects
The COP system is driven by a constant frequency of E
÷ 215. These two bits
specify an additional divide-by value to arrive at the COP timeout rate. These
bits are cleared during reset and can be written only once during the first 64
E-clock cycles after reset in normal modes. The value of these bits is:
4.3 Interrupts
Excluding reset-type interrupts, there are 17 hardware interrupts and one software
interrupt that can be generated from all the possible sources. These interrupts can
be divided into two categories: maskable and non-maskable. Fifteen of the
interrupts can be masked using the I bit of the condition code register (CCR). All
the on-chip (hardware) interrupts are individually maskable by local control bits.
The software interrupt is non-maskable. The external input to the XIRQ pin is
considered a non-maskable interrupt because it cannot be masked by software
once it is enabled. However, it is masked during reset and upon receipt of an
interrupt at the XIRQ pin. Illegal opcode is also a non-maskable interrupt.
Table 4-2 provides a list of the interrupts with a vector location in memory for each,
as well as the actual condition code and control bits that mask each interrupt.
Figure 4-3 shows the interrupt stacking order.
CR1
CR0
E
÷ 215
Divided By
00
1
01
4
10
16
11
64
Table 4-2. Interrupt and Reset Vector Assignments
Vector
Address
Interrupt Source
CCR
Mask
Local
Mask
$FFC0, $FFC1
↓
$FFD4, $FFD5
Reserved
—
$FFD6, $FFD7
SCI serial system:
SCI transmit complete
SCI transmit data register empty
SCI idle line detect
SCI receiver overrun
SCI receive data register full
I bit
TCIE
TIE
ILIE
RIE
$FFD8, $FFD9
SPI serial transfer complete
I bit
SPIE
$FFDA, $FFDB
Pulse accumulator input edge
I bit
PAII
$FFDC, $FFDD
Pulse accumulator overflow
I bit
PAOVI
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