參數(shù)資料
型號： MC68HC711D3MFN3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 129/157頁
文件大?。?/td> 2252K
代理商： MC68HC711D3MFN3
MC68HC711D3 — Rev. 2
Data Sheet
MOTOROLA
Serial Communications Interface (SCI)
73
Data Sheet — MC68HC711D3
Section 6. Serial Communications Interface (SCI)
6.1 Introduction
The serial communications interface (SCI) is a universal asynchronous receiver
transmitter (UART), one of two independent serial input/output (I/O) subsystems in
the MC68HC711D3. It has a standard non-return to zero (NRZ) format (one start,
eight or nine data, and one stop bit). Several baud rates are available. The SCI
transmitter and receiver are independent, but use the same data format and bit
rate.
6.2 Data Format
The serial data format requires these conditions:
An idle line in the high state before transmission or reception of a message
A start bit, logic 0, transmitted or received, that indicates the start of each
character
Data that is transmitted and received least significant bit (LSB) first
A stop bit, logic 1, used to indicate the end of a frame. A frame consists of a
start bit, a character of eight or nine data bits, and a stop bit.
A break, defined as the transmission or reception of a logic 0 for some
multiple number of frames
Selection of the word length is controlled by the M bit in the SCI control register 1
(SCCR1).
6.3 Transmit Operation
The SCI transmitter includes a parallel transmit data register (SCDR) and a serial
shift register that puts data from the SCDR into serial form. The contents of the
serial shift register can only be written through the SCDR. This double-buffered
operation allows a character to be shifted out serially while another character is
waiting in the SCDR to be transferred into the serial shift register. The output of the
serial shift register is applied to PD1 as long as transmission is in progress or the
transmit enable (TE) bit of serial communication control register 2 (SCCR2) is set.
The block diagram, Figure 6-1, shows the transmit serial shift register and the
buffer logic at the top of the figure.
相關(guān)PDF資料
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MCC68HC711D3 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC
MC68HC711D3MP2 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP40
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