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參數(shù)資料
| 型號： | MC68HC705V8FN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 30/172頁 |
| 文件大?。?/td> | 890K |
| 代理商： | MC68HC705V8FN |
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MOTOROLA
SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 114
MC68HC705V8 Specification Rev. 2.1
15.4.2
Rx & Tx SHIFT REGISTERS
The Rx Shift Register gathers received serial data bits from the J1850 bus and makes them
available in parallel form to the Rx Buffer. The Tx Shift Register takes data, in parallel form,
from the Tx Buffer and presents it serially to the State Machine so that it can be transmitted
onto the J1850 bus.
15.4.3
STATE MACHINE
All of the functions associated with performing the protocol are executed or controlled by
the State Machine. The State Machine is responsible for framing, collision detection,
arbitration, CRC generation/checking, and error detection. The following sections describe
the MDLC’s actions in a variety of situations.
15.4.3.1
In-Frame Response
The MDLC does not support the In-Frame Response (IFR) feature of J1850. If the MDLC
receives an IFR, it will ignore the response (not placing it in an Rx Buffer) and wait for the
End of Frame (EOF) symbol.
15.4.3.2
4x Speed Mode
The MDLC can exist on the same J1850 bus as modules which use a special 4x mode of
J1850 VPW operation. The MDLC treats 4x mode messages as noise and ignores them.
The MDLC will wait for a valid SOF or BREAK at 10.4 kbps to resume normal operation.
15.4.3.3
Block Mode
While the MDLC can only transmit a maximum of 12 bytes (including CRC byte) in a given
message, it has the ability to receive a message of unlimited length. Like 4x mode, the
programmer will have to determine from a received message that Block mode is to be
enabled. The programmer then sets the “Receive Block Message” (RXBM) bit in the MDLC
Control Register (MCR) to indicate to the MDLC that the following message will be longer
than 12 bytes and not to treat it as a message over length error.
15.4.3.4
Arbitration
Arbitration is performed by the MDLC simply by comparing the data being received from
the J1850 bus with the data being transmitted. This is done by latching the data being
transmitted into a comparator, where it is compared with the data being received from the
J1850 bus. If a valid data bit is received which has a higher priority over what was
transmitted (0 over 1), arbitration is then lost, and the transmitter stops transmitting until a
valid EOF symbol is received from the J1850 bus. See 15.5.5 MESSAGE ARBITRATION
for more information.
If an invalid bit or a symbol in a non-byte boundary is detected, the transmitter will also stop
transmitting.
In VPW, an active signal will always dominate a passive one, and a shorter passive symbol
will dominate a longer passive symbol. This ensures that a logic zero will dominate a logic
one, and the message with the highest priority (lowest value) will win arbitration. See 15.5.5
MESSAGE ARBITRATION for more details.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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