參數(shù)資料
型號： MC68HC705V8FN
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 172/172頁
文件大小： 890K
代理商： MC68HC705V8FN
MOTOROLA
SECTION 13: PULSE WIDTH MODULATOR
Page 88
MC68HC705V8 Specification Rev. 2.1
13.2.2
PWM DATA REGISTERS
The PWM system has one 8-bit data register which hold the duty cycle for each PWM
output in the least significant 6 bits. The data bits in this register are unaffected by RESET.
Figure 13-6:
PWM Data Register
POL - PWM Polarity
1 = PWM pulse is active high.
0 = PWM pulse is active low.
13.3
PWM DURING WAIT MODE
The PWM continues normal operation during WAIT mode. To decrease power
consumption during WAIT, it is recommended that the rate select bits in the PWM Control
Register be cleared if the PWM is not being used.
13.4
PWM DURING STOP MODE
In STOP mode the oscillator is stopped causing the PWM to cease functioning. Any signal
in process is aborted in whatever phase the signal happens to be in.
13.5
PWM DURING RESET
Upon RESET the PSA0 and PSA1 bits in PWM CONTROL are cleared. This disables the
PWM system and sets the PWMA output low. The user should write to the data registers
prior to enabling the PWM system (for example, prior to setting PSA1 or PSA0). This will
avoid an erroneous duty cycle from being driven.
1
------
-
RESET:
POL
D5
D4
D3
D2
D1
D0
-
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For More Information On This Product,
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