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參數(shù)資料
| 型號： | MC68HC705V8FN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 15/172頁 |
| 文件大?。?/td> | 890K |
| 代理商： | MC68HC705V8FN |
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MOTOROLA
SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 100
MC68HC705V8 Specification Rev. 2.1
15.1.2.2
Reset
This mode is entered from the Power Off mode whenever the MCU supply voltage VDD
rises above the minimum specified value and some MCU reset source is asserted. In order
to prevent an unknown state from being entered and to guarantee correct operation, the
internal MCU reset will be asserted while the MDLC module is being powered up.
This mode is entered from any other mode whenever the MCU supply voltage VDD drops
below the minimum value for correct MDLC operation. When this occurs, the MDLC module
will reenter the Reset mode before being powered down to prevent an unknown state from
being entered.
The Reset mode is also entered from any other mode as soon as one of the MCU’s possible
reset sources (for example, POR, COP watchdog, Reset pin etc.) is asserted.
In this mode, the internal MDLC voltage references are operative, VDD is supplied to the
internal circuits, which are held in their reset state and the internal MDLC system clock is
running. Registers will assume their reset condition. Outputs are held in their programmed
reset state, inputs and network activity are ignored.
15.1.2.3
Run
This mode is entered from the Reset mode after all MCU reset sources are no longer
asserted. It is entered from the MDLC Wait mode whenever a message is successfully
received.
It is entered from the MDLC Stop mode whenever network activity is sensed though
messages will not be received properly until the clocks have stabilized and the CPU is also
in the Run mode.
In this mode, normal network operation takes place. The user should ensure that all MDLC
transmissions have ceased before exiting this mode.
15.1.2.4
MDLC Wait
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a WAIT instruction and if the WCM bit in the MCR register is previously
cleared.
In this mode, the MDLC internal clocks continue to run but the physical interface circuitry is
placed in a low power mode and awaits a valid network message. If a valid network
message is successfully received (RXMS=1) a CPU interrupt request will be generated.
15.1.2.5
MDLC Stop
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a STOP instruction, or if the CPU executes a WAIT instruction and the WCM
bit in the MCR register is previously set.
In this mode, the MDLC internal clocks are stopped but the physical interface circuitry is
placed in a low power mode and awaits network activity. If network activity is sensed, then
a CPU interrupt request will be generated, restarting the MDLC internal clocks.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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