參數(shù)資料
型號(hào)： MC68HC705V8FN
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 147/172頁
文件大小： 890K
代理商： MC68HC705V8FN
SECTION 8: LOW-POWER MODES
MOTOROLA
Page 65
MC68HC705V8 Specification Rev. 2.1
Figure 8-2:
STOP/WAIT Flowcharts
8.1.2
WAIT INSTRUCTION
The WAIT instruction places the MCU in a low-power mode, which consumes more power
than the STOP Mode. In the WAIT Mode the internal processor clock is halted, suspending
all processor and internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the timer or a reset to be generated from the COP
Watchdog Timer. Execution of the WAIT instruction automatically clears the I-bit in the
Condition Code Register. All other registers, memory, and input/output lines remain in their
previous states.
MDLC
Bus
Edge?
Y
N
1.
Fetch Reset Vector
or
2.
Service Interrupt
a.
Stack
b.
Set I-Bit
c.
Vector to Interrupt Routine
WAIT
STOP MOR
bit set?
Y
N
External
RESET?
Y
N
IRQ
External
Interrupt?
Y
N
Stop External Oscillator,
Stop Internal Timer Clock,
and Reset Startup Delay
Restart External Oscillator,
and Stabilization Delay
Stop Internal Processor Clock,
Clear I-Bit in CCR,
End
of Startup
Delay
Y
N
IRQ
External
Interrupt?
Y
N
External Oscillator Active,
and Internal
Timer Clock Active
Restart
Internal Processor Clock
Stop Internal Processor Clock,
Clear I-Bit in CCR,
TIMER
Internal
Interrupt?
Y
N
External
RESET?
Y
N
STOP
MDLC
Bus
Edge?
Y
N
Port A
or C Falling
Edge?
Y
N
Port A
or C Falling
Edge?
Y
N
Reset Chip
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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.
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