- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69028 > MC68HC705V8CFU (FREESCALE SEMICONDUCTOR INC) 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | MC68HC705V8CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 9/172頁 |
| 文件大?。?/td> | 890K |
| 代理商： | MC68HC705V8CFU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁
SECTION 14: SERIAL PERIPHERAL INTERFACE
MOTOROLA
Page 95
MC68HC705V8 Specification Rev. 2.1
WCOL - Write Collision
The write collision bit is set when an attempt is made to write to the serial
peripheral data register while data transfer is taking place. If CPHA is zero, a
transfer is said to begin when SS goes low and the transfer ends when SS goes
high after eight clock cycles on SCK. When CPHA is one, a transfer is said to
begin the first time SCK becomes active while SS is low and the transfer ends
when the SPIF flag gets set. Clearing the WCOL bit is accomplished by reading
the SPSR (with WCOL set) followed by an access to SPDR.
Bit 5 - Not implemented
This bit always reads zero.
MODF - Mode Fault
The mode fault flag indicates that there may have been a multi-master conflict
for system control and allows a proper exit from system operation to a reset or
default system state. The MODF bit is normally clear, and is set only when the
master device has its SS pin pulled low. Setting the MODF bit affects the internal
serial peripheral interface system in the following ways:
An SPI interrupt is generated if SPIE=1.
The SPE bit is cleared. This disables the SPI.
The MSTR bit is cleared, thus forcing the device into the slave mode.
Clearing the MODF bit is accomplished by reading the SPSR (with MODF set),
followed by a write to the SPCR. Control bits SPE and MSTR may be restored
to their original state by user software after the MODF bit has been cleared. It is
also necessary to restore DDRD after a mode fault.
Bits 3-0 - Not Implemented
These bits always read zero.
14.3.3
Serial Peripheral Data I/O Register (SPDR)
The serial peripheral data I/O register is used to transmit and receive data on the serial bus.
Only a write to this register will initiate transmission/reception of another byte, and this will
only occur in the master device. At the completion of transmitting a byte of data, the SPIF
status bit is set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is actually being read.
The first SPIF must be cleared by the time a second transfer of the data from the shift
register to the read buffer is initiated, or an overrun condition will exist. In cases of overrun,
the byte that causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and places data directly into
the shift register for transmission.
SPD7
SPD5
SPD4
SPD3
SPD2
PSD1
SPD0
SPD6
$0C
-
------
-
RESET:
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC705V8B | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| MC68HC705V8FN | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| MC68HC705V8CFN | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| MC68HC705X4CDW | 8-BIT, OTPROM, 2.2 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05X4CDW | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC706P6ACDW | 制造商:Motorola Inc 功能描述: |
| MC68HC708MP16CFU | 制造商:MAJOR 功能描述: |
| MC68HC711D3CFBE2 | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC711D3CFN2 | 功能描述:IC MCU 2MHZ 4K OTP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
| MC68HC711D3CFNE2 | 功能描述:8位微控制器 -MCU 8B OTP 192RAM 2 MHZ RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。