參數(shù)資料
型號： MC68HC705V8CFU
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 123/172頁
文件大?。?/td> 890K
代理商： MC68HC705V8CFU
SECTION 5: INTERRUPTS
MOTOROLA
Page 43
MC68HC705V8 Specification Rev. 2.1
and serviced as specified by the contents of $3FFA and $3FFB.The IRQ timing diagram is
shown in Figure 5-4.
Figure 5-4:
External Interrupts Timing Diagram
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger is
available as a mask option for the IRQ pin only.
5.6
16-BIT TIMER INTERRUPT
There are three different timer interrupt flags that cause a timer interrupt whenever they are
set and enabled. The interrupt flags are in the Timer Status Register (TSR), and the enable
bits are in the Timer Control Register (TCR). Any of these interrupts will vector to the same
interrupt service routine, located at the address specified by the contents of memory
location $3FF8 and $3FF9.
5.7
MDLC INTERRUPT
The MDLC Transmit Message Successful and Receive Message Successful interrupts are
respectively generated by the TXMS and RXMS bits of the MDLC Status Register (MSR).
In addition a wake-up from STOP or WAIT mode can also generate an interrupt from the
MDLC. The MDLC Interrupt Enable (IE) bit is located in the MDLC Control Register (MCR).
Provided the IE bit is set (and the CCR I bit is clear), all interrupts will vector to the same
interrupt service routine, located at the address specified by the contents of memory
location $3FF6 and $3FF7.
5.8
SPI INTERRUPT
There are two different SPI interrupt flags that cause an SPI interrupt whenever they are
set and enabled. The interrupt flags are in the SPI Status Register (SPSR), and the enable
bits are in the SPI Control Register (SPCR). Either of these interrupts will vector to the
IRQ
tILIH
tILIL
tILIH
IRQ1 (Port)
IRQn (Port)
IRQ
(MCU)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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