參數(shù)資料
型號： MC68HC705V8CFU
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 105/172頁
文件大?。?/td> 890K
代理商： MC68HC705V8CFU
SECTION 3: EPROM AND EEPROM
MOTOROLA
Page 27
MC68HC705V8 Specification Rev. 2.1
NOTE:
All options are disabled while the MOR register is being programmed.
(MORON=LATCH=EPGM=1 in EPROM Programming Register with the
exception of the REGEN bit.)
3.4
EEPROM PROGRAMMING REGISTER $1C
The contents and use of the programming register are discussed below.
Figure 3-4:
Programming Register
NOTE:
Any reset including LVR will abort any write in progress when it is
asserted. Data written to the addressed byte will therefore be
indeterminate.
3.4.1
CPEN - Charge Pump Enable
When set, CPEN enables the charge pump which produces the internal programming
voltage. This bit should be set with the LATCH bit. The programming voltage will not be
available until EEPGM is set. The charge pump should be disabled when not in use. CPEN
is readable and writable and is cleared by reset.
3.4.2
ER1:ER0 - Erase Select Bits
ER1 and ER0 form a 2-bit field which is used to select one of three erase modes: byte,
block, or bulk. Table 3-2 shows the modes selected for each bit configuration. These bits
are readable and writable and are cleared by reset.
In byte erase mode, only the selected byte is erased. In block mode, a 32-byte block of
EEPROM is erased. The EEPROM memory space is divided into four 32-byte blocks
($0240-$025F, $0260-$027F, $0280-$029F, $02A0-$02BF), and doing a block erase to
any address within a block will erase the entire block. In bulk erase mode, the entire 128
byte EEPROM section is erased.
-
ER1
ER0
LATCH
EERC
EEPGM
CPEN
$1C
0
000000
0
RESET:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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