參數(shù)資料
型號: MC68HC705V8CFU
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁數(shù): 37/172頁
文件大小: 890K
代理商: MC68HC705V8CFU
MOTOROLA
SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 120
MC68HC705V8 Specification Rev. 2.1
15.5.2.4
EOD - End of Data Symbol
The EOD symbol is a short passive period on the J1850 bus used to signify to any
recipients of a message that the transmission by the originator has completed.
15.5.2.5
IFR - In Frame Response Bytes
The IFR section of the J1850 message format is optional. The MDLC does not support this
option. The MDLC will not transmit an IFR under any circumstances. If an IFR is received
from another node, the MDLC will ignore this part of the message and wait for the EOF
symbol before resuming normal operation.
15.5.2.6
EOF - End of Frame Symbol
This symbol is a passive period on the J1850 bus, longer than an EOD symbol, which
signifies the end of a message. Since an EOF symbol is longer than an EOD symbol, if no
response is transmitted after an EOD symbol, it becomes an EOF, and the message is
assumed to be completed.
15.5.2.7
IFS - Inter-Frame Separation Symbol
The IFS symbol is a passive period on the J1850 bus that allows proper synchronization
between nodes during continuous message transmission. The IFS symbol is transmitted
by a node following the completion of the EOF period.
When the last byte of a message has been transmitted onto the J1850 bus, and the EOF
symbol time has expired, all nodes must then wait for the IFS symbol time to expire before
transmitting an SOF, marking the beginning of another message.
However, if the MDLC is waiting for the IFS period to expire before beginning a
transmission and a rising edge is detected before the IFS time has expired, it must
internally synchronize to that edge. If a write to the MTCR register (initiate transmission)
occurred on or before 104
t
MDLC from the received rising edge, then the MDLC will transmit
and arbitrate for the bus. If a CPU write to the MTCR register occurred after 104
t
MDLC from
the detection of the rising edge, then the MDLC will not transmit, but will wait for the next
IFS period to expire before attempting to transmit the message.
A rising edge may occur during the IFS period because of varying clock tolerances and
loading of the J1850 bus, causing different nodes to observe the completion of the IFS
period at different times. Receivers must synchronize to any SOF occurring during an IFS
period to allow for individual clock tolerances.
15.5.2.8
BREAK - Break
Any MDLC transmitting at the time a BREAK is detected will treat the BREAK as if a loss
of arbitration had occurred, and halt transmission. The MDLC cannot transmit a BREAK
symbol. If while receiving a message the MDLC detects a BREAK symbol, it will treat the
BREAK as a reception error and clear any partially received message from the Rx buffer.
15.5.2.9
Idle Bus
An idle condition exists on the bus during any passive period after expiration of the IFS
period. Any node sensing an idle bus condition can begin transmission immediately.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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