參數(shù)資料
型號： MC68HC705T16B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： PLASTIC, SDIP-56
文件頁數(shù)： 95/128頁
文件大?。?/td> 734K
代理商： MC68HC705T16B
MC68HC05T16
MOTOROLA
8-3
PULSE WIDTH MODULATOR
8
low cycle. A value of $7F results in a 50% duty cycle. The maximum value of $FF results in a
255/256 duty cycle. The 14-bit PWM period is 256x0.476
s=121.9s for a CPU clock of 2.1MHz.
The 6-bit register acts as a binary rate multiplier (BRM). The value set in this register (powers of 2)
equals the number of pulses (pulse width equals to the PWM driving clock cycle) equally
distributed in a 64-PWM-cycle. A maximum value of $2x will have 32 pulses equally distributed in
64 PWM cycles (64 cycles has a period of 64x121.9
s=7.8ms).
Combining the 8-bit PWM together with the 6-bit BRM, the total average duty cycle at the output
will be (M+N/64)/256, where M is the content of the 8-bit high-order register, and N is the content
of the 6-bit low-order register. Using this mechanism, a true 14-bit resolution PWM is achieved.
Figure 8-2 shows the waveform for the 14-bit PWM channel. Note that the resulting waveform is
periodic on every 64 PWM cycles.
Figure 8-2 14-Bit PWM Output Waveform
M=$00
256T
M=$01
M=$7F
M=$FF
T=1 CPU clock period (0.476
s if CPU clock=2.1MHz)
Pulse inserted at end of PWM cycle
N
PWM cycles where pulses are inserted in a 64-cycle frame
Number of inserted
pulses in a 64-cycle
--xxxxx1
32
1
--xxxx1x
16, 48
2
--xxx1xx
8, 24, 40, 56
4
--xx1xxx
4, 12, 20, 28, 36, 44, 52, 60
8
--x1xxxx
2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
16
--1xxxxx
1, 3, 5, 7, ......61, 63
32
255T
128T
255T
T
M = value set in 8-bit PWM register (address $36)
N = value set in 6-bit binary rate multiplier (address $35)
T
depends on setting of N.
TPG
67
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PDF描述
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