參數(shù)資料
型號： MC68HC705T16B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： PLASTIC, SDIP-56
文件頁數(shù)： 58/128頁
文件大小： 734K
代理商： MC68HC705T16B
MC68HC05T16
MOTOROLA
4-5
RESETS AND INTERRUPTS
4
4.2.1
Hardware Controlled Sequences
The following three functions are not strictly interrupts, however, they are tied very closely to the
interrupts. These functions are RESET, STOP, WAIT.
1) RESET
The RESET input pin causes the program to go to its starting
address. This address is specied by the contents of memory
locations $FFFE and $FFFF. The interrupt mask of the condition
code register is also set. Most parts of the MCU is congured to
some known state as described in Table 4-1.
2) STOP
The STOP instruction causes the oscillator to be turned off and
the processor “sleeps” until an external interrupt (IRQ) or RESET
occurs. See section 12 on Low Power Modes.
3) WAIT
The WAIT instruction causes all processor clocks to stop, but
leaves the Timer and PAC clocks running. This “rest” state of the
processor can be exited by RESET, an external interrupt (IRQ),
or any of the interrupts described above. There are no special
wait vectors for these individual interrupts. See section 12 on
Low Power Modes.
Table 4-2 Reset/Interrupt Vector Addresses
Register
Flag Name
Interrupt
CPU Interrupt
Vector Address
–
Reset
RESET
$FFFE-$FFFF
–
Software
SWI
$FFFC-$FFFD
OSD Status
VFLB
Vertical Flyback
OSD
$FFFA-$FFFB
R3CF/R2CF/
R1CF/R0CF
OSD Row Completion
–
External Interrupt
IRQ
$FFF8-$FFF9
Timer Status
ICF
Input Capture
TIMER
$FFF6-$FFF7
OC0F/OC1F
Output Compare
TOF
Timer Overow
M-Bus Status
ALOST
Arbitration Loss
M-BUS
$FFF4-$FFF5
SELTED
Addressed as Slave
MCF
Transfer Complete
PAC Control
PAOF
Pulse Accumulator Overow
PAC
$FFF2-$FFF3
Multi-Function
Timer
RTIF
Real Time Interrupt
MFT
$FFF0-$FFF1
TOF
Timer Overow
TPG
33
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