參數(shù)資料
型號： MC68HC705T16B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： PLASTIC, SDIP-56
文件頁數(shù)： 91/128頁
文件大?。?/td> 734K
代理商： MC68HC705T16B
MC68HC05T16
MOTOROLA
7-1
PULSE ACCUMULATOR
7
PULSE ACCUMULATOR
The Pulse Accumulator is an 8-bit counter that can operate in either of two modes; event counting
mode and the gated time accumulation mode. The operating mode is selected by a control bit in
the Pulse Accumulator Control register.
In the event counting mode, the 8-bit counter is clocked by the signal on the PACIN pin. The
maximum clocking rate for the external counting mode is E (CPU) clock divided by two.
In the gated time accumulation mode, the 8-bit counter is driven by E clock divided by 64. The
counter will increment when PACIN pin is high and halt when PACIN is low.
7.1
Pulse Accumulator Registers
Two registers are associated with the Pulse Accumulator; they are described below.
7.1.1
PAC Control and Status Register (PACTL)
Register bit denitions:
PAOF - PAC Overow Interrupt Flag Bit.
1 (set)
–
A PAC overow from $FF to $00 has occurred.
0 (clear) –
No PAC overow has occurred.
It is set when the count in the pulse accumulator rolls over from $FF to $00. PAOF is cleared by
writing a “0” to the bit. An interrupt to the CPU is generated if the PAIE bit is set.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0E
PAOF
PAEN
PAMOD
PAIE
0000 0000
TPG
63
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