參數(shù)資料
型號： MC68HC705T16B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： PLASTIC, SDIP-56
文件頁數(shù)： 64/128頁
文件大小： 734K
代理商： MC68HC705T16B
MOTOROLA
4-10
MC68HC05T16
RESETS AND INTERRUPTS
4
4.2.6
PAC Interrupt
Pulse Accumulator interrupt is enabled when the enable bit, PAIE of PAC Control register is set.
The interrupt service routine address for PAC is specied by the contents of memory location
$FFF2 and $FFF3.
PAOF - PAC Overow Interrupt Flag Bit.
1 (set)
–
A PAC overow from $FF to $00 has occurred.
0 (clear) –
No PAC overow has occurred.
It is set when the count in the pulse accumulator rolls over from $FF to $00. PAOF is cleared by
writing a “0” to the bit. An interrupt to the CPU is generated if the PAIE bit is set.
PAIE - PAC Interrupt Enable Bit
1 (set)
–
PAC overow Interrupt enabled.
0 (clear) –
PAC overow Interrupt disabled.
Refer to section 7 for detailed description of Pulse Accumulator.
4.2.7
OSD Interrupts
There are ve OSD interrupt sources, VFLBK bit and R0/1/2/3CF bits of OSD Status register, in
the OSD module. VFLB bit will be set whenever the leading edge of vertical yback pin, VFLBK,
has been detected. An interrupt will occur if the corresponding interrupt enable bit, VFINTE, is set.
Whenever each row terminates its display, RiCF bit will be set and an interrupt will be generated
provided that the corresponding interrupt enable bit, RiINTE is set. The interrupt service routine
address is specied by the contents of memory location $FFFA and $FFFB.
VFINTE - VFLBK interrupt enable
1 (set)
–
Vertical yback interrupt enabled.
0 (clear) –
Vertical yback interrupt disabled.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
PACTL
$0E
PAOF
PAEN PAMOD PAIE
0000 0000
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Frame Control 3 and Status
$2B
VFINTE MUTE1 MUTE0 VFLB
R3CF
R2CF
R1CF
R0CF 0000 0000
TPG
38
相關(guān)PDF資料
PDF描述
MC68HC05T16B 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
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