參數(shù)資料
型號： MC68HC11D0CFNE3R
廠商： Freescale Semiconductor
文件頁數(shù)： 71/124頁
文件大?。?/td> 0K
描述： MCU 8-BIT 192 RAM 3MHZ 44-PLCC
標準包裝： 450
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 3MHz
連通性： SCI，SPI
外圍設備： POR，WDT
輸入/輸出數(shù)： 26
程序存儲器類型： ROMless
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 帶卷 (TR)
RESETS AND INTERRUPTS
5-6
TECHNICAL DATA
5.2.7 COP
The COP watchdog system is enabled if the NOCOP control bit in the CONFIG regis-
ter is clear, and disabled if NOCOP is set. The COP rate is set for the shortest duration
time-out.
5.2.8 SCI
The reset condition of the SCI system is independent of the operating mode. At reset,
the SCI baud rate is indeterminate and must be established by a software write to the
BAUD register. All transmit and receive interrupts are masked and both the transmitter
and receiver are disabled so the port pins default to being general-purpose I/O lines.
The SCI frame format is initialized to an 8-bit character size. The send break and re-
ceiver wake-up functions are disabled. The TDRE and TC status bits in the SCI status
register are both set, indicating that there is no transmit data in either the transmit data
register or the transmit serial shift register. The RDRF, IDLE, OR, NF, and FE receive-
related status bits are cleared.
5.2.9 SPI
The SPI system is disabled by reset. The port pins associated with this function default
to being general-purpose I/O lines.
5.2.10 System
The memory system is configured for normal read operation. PSEL[3:0] are initialized
with the value $0101, causing the external IRQ pin to have the highest I-bit interrupt
priority. The IRQ pin is configured for level sensitive operation (for wired-OR systems).
The RBOOT, SMOD, and MDA bits in the HPRIO register reflect the status of the
MODB and MODA inputs at the rising edge of reset. The DLY control bit in OPTION is
set to specify that an oscillator start-up delay is imposed upon recovery from STOP.
The clock monitor system is disabled by CME equals zero.
5.3 Reset and Interrupt Priority
Resets and interrupts have a hardware priority that determines which reset or interrupt
is serviced first when simultaneous requests occur. Any maskable interrupt can be giv-
en priority over other maskable interrupts.
The first six interrupt sources are not maskable. The priority arrangement for these
sources is as follows:
1.
POR or RESET pin
2.
Clock monitor reset
3.
COP watchdog reset
4. XIRQ interrupt
5. Illegal opcode interrupt
6. Software interrupt (SWI)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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