參數(shù)資料
型號: MC68HC11D0CFNE3R
廠商: Freescale Semiconductor
文件頁數(shù): 123/124頁
文件大?。?/td> 0K
描述: MCU 8-BIT 192 RAM 3MHZ 44-PLCC
標準包裝: 450
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 3MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 26
程序存儲器類型: ROMless
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 帶卷 (TR)
TIMING SYSTEM
9-12
TECHNICAL DATA
PR[1:0] — Timer Prescaler Select
These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0]
can only be written once, and the write must be within 64 cycles after reset. Refer to
Table 9-1 for specific timing values.
9.3.10 Timer Interrupt Flag 2 Register
Bits in this register indicate when certain timer system events have occurred. Coupled
with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to
operate in either a polled or interrupt driven system. Each bit of TFLG2 corresponds
to a bit in TMSK2 in the same position.
Clear flags by writing a one to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time (Periodic) Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits [3:0]— Not implemented
Always read zero
9.4 Real-Time Interrupt
The real-time interrupt feature, used to generate hardware interrupts at a fixed periodic
rate, is controlled and configured by two bits (RTR1 and RTR0) in the pulse accumu-
lator control (PACTL) register. The RTII bit in the TMSK2 register enables the interrupt
capability. The four different rates available are a product of the MCU oscillator fre-
quency and the value of bits RTR[1:0]. Refer to the following table, which shows the
periodic real-time interrupt rates.
PR[1:0]
Prescaler
0 0
1
0 1
4
1 0
8
1 1
16
TFLG2 — Timer Interrupt Flag 2
$0025
Bit 7
654321
Bit 0
TOF
RTIF
PAOVF
PAIF
0
RESET:
0000000
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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