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參數(shù)資料
| 型號： | MC68HC11C0FN3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 3 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 40/76頁 |
| 文件大?。?/td> | 394K |
| 代理商： | MC68HC11C0FN3 |
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MOTOROLA
MC68HC11C0
45
MC68HC11C0TS/D
OC1I –OC4I — Output Compare x Interrupt Enable
If the OCxF flag bit is set while the OCxI enable bit is set, a hardware interrupt sequence is requested.
I4/O5I — Input Capture 4 or Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt bit. When I4/O5 in PACTL is zero,
I4/O5I is the output compare 5 interrupt control bit.
IC1I –IC3I — Input Capture x Interrupt Enable
If the ICxF flag bit is set while the ICxI enable bit is set, a hardware interrupt sequence is requested.
NOTE
Control bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1
enable the corresponding interrupt sources.
Clear flags by writing a one to the corresponding bit position(s).
OC1F –OC4F — Output Compare x Flag
Set each time the counter matches output compare x value
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on which function was enabled by I4/O5 of PACTL
IC1F –IC3F — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
TCTL2 — Timer Control 2
$0021
Bit 7
654321
Bit 0
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
RESET:
00000000
Table 9 Timer Control Configuration
EDGxB
EDGxA
Configuration
0
Capture disabled
0
1
Capture on rising edges only
1
0
Capture on falling edges only
1
Capture on any edge
TMSK1 — Timer Interrupt Mask 1
$0022
Bit 7
654321
Bit 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
RESET:
00000000
TFLG1 — Timer Interrupt Flag 1
$0023
Bit 7
654321
Bit 0
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
RESET:
00000000
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