
MC68HC11C0
MOTOROLA
MC68HC11C0TS/D
27
5 Parallel Input/Output
The MC68HC11C0 has up to 35 input/output lines, depending on the operating mode. The address and
data bus have no associated ports and cannot be used for general-purpose I/O.
Pins on all ports except port E have selectable on-chip pull-up devices. A single bit in the port pull-up
assignment register (PPAR) enables the pull-up devices for all pins on the associated port. A pin's pull-
up device is active only when the associated data direction bit configures that pin as an input. Pull-ups
for IRQ and XIRQ are active whenever port D pull-ups are enabled. Port G pull-ups are enabled out of
reset in order to provide a logic level one on all chip select and memory expansion address lines. Port
F pull-ups are also enabled out of reset and are active only when a port F pin is configured as an input.
Refer to the PPAR register description.
Port A has eight fully bidirectional I/O pins. Port A shares functions with the timer system. Note that
when PA7 is configured as an output (DDA7 = 1) it is still the input to the pulse accumulator (PAI).
Port D shares functions with the serial systems (SCI and SPI). Because IRQ and XIRQ are now asso-
ciated functions of port D, a new port D I/O control register (DIOCTL) has been added. Port D functions
are controlled by a combination of DIOCTL bits, data direction bits, SCI and SPI enable bits. Refer to
the PORTD description. Port D has six bidirectional pins and one output-only pin.
Port E is a four-bit input-only port that shares functions with the A/D converter system. If the A/D system
is not being used, port F pins can be used as general-purpose inputs.
Port F has seven bidirectional pins and shares functions with the keyboard interrupt inputs. Port F pins
not used for interrupt request inputs can be used for general-purpose I/O.
Port G is an eight-bit fully bidirectional I/O port. Port G shares functions with the memory expansion ad-
dress lines and the chip selects. Pins not used for memory expansion address or chip select can be
used for general-purpose I/O.
Port H is a two-bit bidirectional port. Port H pins also serve as outputs for the two-channel PWM timer.
The following table is a summary of the configuration and features of each port.
Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at
reset. Port pins are either driven to a specified logic level or are configured as high impedance inputs.
I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the
corresponding latches are dependent upon the electrical state of the pins during reset. In port descrip-
tions, an “I” indicates this condition. Port pins that are driven to a known logic level during reset are
shown with a value of either one or zero. Some control bits are unaffected by reset. Reset states for
these bits are indicated with a “U”.
Port
Input
Pins
Output
Pins
Bidirectional
Pins
On-Chip
Pull-Up Devices
Shared Functions
Port A
—
8
Yes
Timer
Port D
—
1
6
Yes
SCI, SPI, IRQ, and XIRQ
Port E
4
—
No
A/D Converter
Port F
—
7
Yes
Keyboard Interrupt Requests
Port G
—
8
Yes
Memory Expansion Address and
Chip Selects
Port H
—
2
Yes
PWM Timer