參數(shù)資料
型號(hào): MC68HC11A8VCFU2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: HCMOS Single-Chip Microcontroller
中文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁(yè)數(shù): 89/158頁(yè)
文件大小: 776K
代理商: MC68HC11A8VCFU2
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MC68HC11A8
TECHNICAL DATA
RESETS, INTERRUPTS, AND LOW POWER MODES
MOTOROLA
9-9
9
9.2.1 Software Interrupt (SWI)
The software interrupt is executed in the same manner as any other instruction and
will take precedence over interrupts only if the other interrupts are masked (I and X bits
in the condition code register set). The SWI instruction is executed in a manner similar
to other maskable interrupts in that it sets the I bit, CPU registers are stacked, etc.
NOTE
The SWI instruction will not be fetched if an interrupt is pending.
However, once an SWI instruction has begun, no interrupt can be
honored until the SWI vector has been fetched.
Figure 9-3 Interrupt Stacking Order
9.2.2 Illegal Opcode Trap
Since not all possible opcodes or opcode sequences are defined, an illegal opcode de-
tection circuit has been included. When an illegal opcode is detected, an interrupt is
requested to the illegal opcode vector. The illegal opcode vector should never be left
uninitialized. It is a good idea to reinitialize the stack pointer as a result of an illegal
opcode interrupt so repeated execution of illegal opcodes does not cause stack over-
runs.
9.2.3 Interrupt Mask Bits in Condition Code Register
Upon reset, both the X bit and the I bit are set to inhibit all maskable interrupts and
XIRQ. After minimum system initialization, software may clear the X bit by a TAP in-
struction, thus enabling XIRQ interrupts. Thereafter software cannot set the X bit so
an XIRQ interrupt is effectively a nonmaskable interrupt. Since the operation of the I
Table 9-4 SCI Serial System Interrupts
Interrupt Cause
Receive Data Register Full
Receiver Overrun
Idle Line Detect
Transmit Data Register Empty
Transmit Complete
Local Mask
RIE
RIE
ILIE
TIE
TCIE
PCL
PCH
IYL
IYH
IXL
IXH
ACCA
ACCB
CCR
SP
— SP BEFORE INTERRUPT
SP–1
SP–2
SP–3
SP–4
SP–5
SP–6
SP–7
SP–8
SP–9
— SP AFTER INTERRUPT
7
0
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