參數(shù)資料
型號： MC68HC11A8VCFU2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 139/158頁
文件大?。?/td> 776K
代理商： MC68HC11A8VCFU2
MC68HC11A8
TECHNICAL DATA
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-19
A
NOTES:
1.Formula only for dc to 2 MHz.
2.Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock
duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following
expressions in place of 1/8 t
cyc
in the above formulas, where applicable:
(a) (1-DC) x 1/4 t
cyc
(b) DC x 1/4 t
cyc
Where:
DC is the decimal value of duty cycle percentage (high time).
3.All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise noted.
Table A-7 Expansion Bus Timing
V
DD
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
Characteristic
Num
Symbol
1.0 MHz
Min
dc
1000
477
2.0 MHz
Min
dc
500
227
3.0 MHz
Min
dc
333
146
Unit
Max
1.0
—
—
Max
2.0
—
—
Max
3.0
—
—
Frequency of Operation (E-Clock Frequency)
Cycle Time
Pulse Width, E Low
PW
EL
= 1/2 t
cyc
– 23 ns(Note 1)
Pulse Width, E High
PW
EH
= 1/2 t
cyc
– 28 ns(Note 1)
E and AS Rise and Fall Time
f
o
MHz
ns
ns
1
2
t
cyc
PW
EL
3
PW
EH
472
—
222
—
141
—
ns
4a, b
t
r
t
f
—
20
20
—
—
20
20
—
—
20
15
—
ns
9
Address Hold Time
t
AH
= 1/8 t
cyc
– 29.5 ns (Note 1, 2a)
Non-Muxed Address Valid Time to E Rise
t
AV
= PW
EL
– (t
ASD
+ 80 ns)(Note 1, 2a)
Read Data Setup Time
Read Data Hold Time (Max = t
MAD
)
Write Data Delay Time
t
DDW
= 1/8 t
cyc
+ 65.5 ns (Note 1, 2a)
Write Data Hold Time
t
DHW
= 1/8 t
cyc
– 29.5 ns(Note 1, 2a)
Muxed Address Valid Time to E Rise
t
AVM
= PW
EL
– (t
ASD
+ 90 ns)(Note 1, 2a)
Muxed Address Valid Time to AS Fall
t
ASL
= PW
ASH
– 70 ns(Note 1)
Muxed Address Hold Time
t
AHL
= 1/8 t
cyc
– 29.5 ns(Note 1, 2b)
Delay Time, E to AS Rise
t
ASD
= 1/8 t
cyc
– 9.5 ns (Note 1, 2a)
Pulse Width, AS High
PW
ASH
= 1/4 t
cyc
– 29 ns(Note 1)
Delay Time, AS to E Rise
t
ASED
= 1/8 t
cyc
– 9.5 ns(Note 1, 2b)
MPU Address Access Time(Note 2a)
t
ACCA
= t
cyc
– (PW
EL
– t
AVM
) – t
DSR
– t
f
MPU Access Time
t
ACCE
= PW
EH
– t
DSR
Muxed Address Delay
(Previous Cycle MPU Read)
t
MAD
= t
ASD
+ 30 ns(Note 1, 2a)
t
AH
95.5
33
26
ns
12
t
AV
281.5
—
94
—
54
—
ns
17
18
19
t
DSR
t
DHR
t
DDW
30
0
—
—
30
0
—
—
83
128
30
0
—
—
51
71
ns
ns
ns
145.5
190.5
21
t
DHW
95.5
—
33
—
26
—
ns
22
t
AVM
271.5
—
84
—
54
—
ns
24
t
ASL
151
—
26
—
13
—
ns
25
t
AHL
95.5
—
33
—
31
—
ns
26
t
ASD
115.5
—
53
—
31
—
ns
27
PW
ASH
221
—
96
—
63
—
ns
28
t
ASED
115.5
—
53
—
31
—
ns
29
t
ACCA
744.5
—
307
—
196
—
ns
35
t
ACCE
—
442
—
192
—
111
ns
36
t
MAD
145.5
—
83
—
51
—
ns
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