MC68HC11A8
TECHNICAL DATA
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
10-11
10
**Infinity or Until Reset Occurs
***12 Cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer
number of MPU E-clock cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch
the appropriate interrupt vector (14 + n total).
dd
= 8-Bit Direct Address ($0000 –$00FF) (High Byte Assumed to be $00)
ff
= 8-Bit Positive Offset $00 (0) to $FF (255) (Is Added to Index)
hh
= High Order Byte of 16-Bit Extended Address
ii
= One Byte of Immediate Data
jj
= High Order Byte of 16-Bit Immediate Data
kk
= Low Order Byte of 16-Bit Immediate Data
ll
= Low Order Byte of 16-Bit Extended Address
mm
= 8-Bit Bit Mask (Set Bits to be Affected)
rr
= Signed Relative Offset $80 (– 128) to $7F (+ 127)
(Offset Relative to the Address Following the Machine Code Offset Byte)
TEST
TPA
TST (opr)
TEST (Only in Test Modes)
Transfer CC Register to A
Test for Zero or Minus
Address Bus Counts
CCR
→
A
M – 0
INH
INH
EXT
IND,X
IND,Y
A INH
B INH
INH
INH
INH
INH
INH
INH
INH
00
07
7D
6D
1
1
3
2
3
1
1
1
2
1
2
1
1
2
**
2
6
6
7
2
2
3
4
3
4
***
3
4
2-20
2-1
5-9
6-4
7-4
2-1
2-1
2-3
2-5
2-2
2-4
2-16
2-2
2-4
- - - - - - - -
- - - - - - - -
- - - -
¤ ¤
0 0
18 6D
hh ll
ff
ff
TSTA
TSTB
TSX
TSY
TXS
TYS
WAI
XGDX
XGDY
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation.
Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
A – 0
B – 0
SP + 1
→
IX
SP + 1
→
IY
IX – 1
→
SP
IY – 1
→
SP
Stack Regs & WAlT
IX
→
D, D
→
IX
IY
→
D, D
→
IY
4D
5D
30
- - - -
¤ ¤
0 0
- - - -
¤ ¤
0 0
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
Transfer Stack Pointer to X
Transfer Stack Pointer to Y
Transfer X to Stack Pointer
Transfer Y to Stack Pointer
Wait for Interrupt
Exchange D with X
Exchange D with Y
18 30
35
18 35
3E
8F
18 8F
Table 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times
(Sheet 6 of 6)
Source
Form(s)
Operation
Boolean Expression
Addressing
Mode for
Operand
Machine Coding
(Hexadecimal)
Opcode
B
C
Cycle
by
Cycle*
Condition Codes
Operand(s)
S X H I N Z V C