Serial Peripheral Interface Module (SPI)
Error conditions
MC68HC08AZ32
MOTOROLA
Serial Peripheral Interface Module (SPI)
225
If ERRIE = ‘1’, the SPI generates an SPI receiver/error CPU
interrupt request.
The SPE bit is cleared.
The SPTE bit is set.
The SPI state counter is cleared.
The data direction register of the shared I/O port regains control of
port drivers.
NOTE:
To prevent bus contention with another master SPI after a mode fault
error, clear all SPI bits of the data direction register of the shared I/O
port.
NOTE:
Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit
has no function when SPE = ‘0’. Reading SPMSTR when MODF = ‘1’
shows the difference between a MODF occurring when the SPI is a
master and when it is a slave.
When configured as a slave (SPMSTR = ‘0’), the MODF flag is set if SS
goes high during a transmission. When CPHA = ‘0’, a transmission
begins when SS goes low and ends once the incoming SPSCK goes
back to its idle level following the shift of the eighth data bit. When CPHA
= ‘1’, the transmission begins when the SPSCK leaves its idle level and
SS is already low. The transmission continues until the SPSCK returns
to its IDLE level following the shift of the last data bit. See
Transmission
formats
on page 217.
NOTE:
When CPHA = ‘0’, a MODF occurs if a slave is selected (SS is at ‘0’) and
later unselected (SS is ‘1’) even if no SPSCK is sent to that slave. This
happens because SS at ‘0’ indicates the start of the transmission (MISO
driven out with the value of MSB) for CPHA = ‘0’. When CPHA = ‘1’, a
slave can be selected and then later unselected with no transmission
occurring. Therefore, MODF does not occur since a transmission was
never begun.
In a slave SPI (MSTR = ‘0’), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by toggling the SPE bit of the slave.
17-spi