Byte Data Link Controller-Digital (BDLC-D)
Data Sheet
MC68HC08AS32A — Rev. 1
78
Byte Data Link Controller-Digital (BDLC-D)
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MOTOROLA
Valid SOF Symbol
In
Figure 4-11
(4)
, if the active-to-passive received transition beginning the next
data bit (or symbol) occurs between
c
and
d
, the current symbol would be
considered a valid SOF symbol.
Valid BREAK Symbol
In
Figure 4-12
, if the next active-to-passive received transition does not occur
until after
e
, the current symbol will be considered a valid BREAK symbol. A
BREAK symbol should be followed by a start-of-frame (SOF) symbol beginning
the next message to be transmitted onto the J1850 bus. See
4.4.2 J1850 Frame
Format
for BDLC response to BREAK symbols.
Figure 4-12. J1850 VPW Received BREAK Symbol Times
4.4.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a non-destructive
manner, allowing the message with the highest priority to be transmitted, while any
transmitters which lose arbitration simply stop transmitting and wait for an idle bus
to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that another
message is in progress, it waits until the bus is idle. However, if multiple nodes
begin to transmit in the same synchronization window, message arbitration will
occur beginning with the first bit after the SOF symbol and will continue with each
bit thereafter.
The variable pulse width modulation (VPW) symbols and J1850 bus electrical
characteristics are chosen carefully so that a logic 0 (active or passive type) will
always dominate over a logic 1 (active or passive type) that is simultaneously
transmitted. Hence, logic 0s are said to be dominant and logic 1s are said to be
recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted a
recessive bit, the node loses arbitration and immediately stops transmitting. This is
known as bitwise arbitration.
(2) VALID BREAK SYMBOL
240
μ
s
e
ACTIVE
PASSIVE
F
Freescale Semiconductor, Inc.
n
.