Central Processor Unit (CPU)
Data Sheet
MC68HC08AS32A — Rev. 1
132
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
RTI
Return from Interrupt
SP
←
(SP) + 1; Pull (CCR)
SP
←
(SP) + 1; Pull (A)
SP
←
(SP) + 1; Pull (X)
SP
←
(SP) + 1; Pull (PCH)
SP
←
(SP) + 1; Pull (PCL)
INH
80
7
RTS
Return from Subroutine
SP
←
SP + 1
;
Pull
(
PCH)
SP
←
SP + 1; Pull (PCL)
– – – – – – INH
81
4
SBC #
opr
SBC
opr
SBC
opr
SBC
opr
,X
SBC
opr
,X
SBC ,X
SBC
opr
,SP
SBC
opr
,SP
Subtract with Carry
A
←
(A) – (M) – (C)
– –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
SEC
Set Carry Bit
C
←
1
– – – – – 1 INH
99
1
SEI
Set Interrupt Mask
I
←
1
– – 1 – – – INH
9B
2
STA
opr
STA
opr
STA
opr
,X
STA
opr
,X
STA ,X
STA
opr
,SP
STA
opr
,SP
Store A in M
M
←
(A)
0 – –
–
DIR
EXT
IX2
IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
STHX
opr
Store H:X in M
(M:M + 1)
←
(H:X)
0 – –
– DIR
35
dd
4
STOP
Enable IRQ Pin; Stop Oscillator
I
←
0; Stop Oscillator
– – 0 – – – INH
8E
1
STX
opr
STX
opr
STX
opr
,X
STX
opr
,X
STX ,X
STX
opr
,SP
STX
opr
,SP
Store X in M
M
←
(X)
0 – –
–
DIR
EXT
IX2
IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
SUB #
opr
SUB
opr
SUB
opr
SUB
opr
,X
SUB
opr
,X
SUB ,X
SUB
opr
,SP
SUB
opr
,SP
Subtract
A
←
(A) – (M)
– –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
SWI
Software Interrupt
PC
←
(PC) + 1; Push (PCL)
SP
←
(SP) – 1; Push (PCH)
SP
←
(SP) – 1; Push (X)
SP
←
(SP) – 1; Push (A)
SP
←
(SP) – 1; Push (CCR)
SP
←
(SP) – 1; I
←
1
PCH
←
Interrupt Vector High Byte
PCL
←
Interrupt Vector Low Byte
– – 1 – – – INH
83
9
TAP
Transfer A to CCR
CCR
←
(A)
INH
84
2
TAX
Transfer A to X
X
←
(A)
– – – – – – INH
97
1
TPA
Transfer CCR to A
A
←
(CCR)
– – – – – – INH
85
1
Table 7-1. Instruction Set Summary (Sheet 6 of 7)
Source
Form
Operation
Description
Effect
on CCR
A
M
O
O
C
V H I N Z C
F
Freescale Semiconductor, Inc.
n
.