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Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
MC68HC08AS32A — Rev. 1
Data Sheet
MOTOROLA
Clock Generator Module (CGM)
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115
The K factor in the equations is derived from internal PLL parameters. K
ACQ
is the
K factor when the PLL is configured in acquisition mode, and K
TRK
is the K factor
when the PLL is configured in tracking mode. (See
5.3.2.2 Acquisition and
Tracking Modes
.)
V
f
RDV
NOTE:
There is an inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are quantized
into units based on the reference frequency. (See
5.3.2.3 Automatic and Manual
PLL Bandwidth Modes
.) A certain number of clock cycles, n
ACQ
, is required to
ascertain that the PLL is within the tracking mode entry tolerance,
TRK
, before
exiting acquisition mode. Additionally, a certain number of clock cycles, n
TRK
, is
required to ascertain that the PLL is within the lock mode entry tolerance,
L
ock
.
Therefore, the acquisition time, t
ACQ
, is an integer multiple of n
ACQ
/f
RDV
, and the
acquisition to lock time, t
AL
, is an integer multiple of n
TRK
/f
RDV
. Refer to
5.3.2
Phase-Locked Loop Circuit (PLL)
for the value of f
RDV
. Also, since the average
frequency over the entire measurement period must be within the specified
tolerance, the total time usually is longer than t
L
ock
as calculated above.
In manual mode, it is usually necessary to wait considerably longer than t
L
ock
before selecting the PLL clock (see
5.3.3 Base Clock Selector Circuit
), because
the factors described in
5.9.2 Parametric Influences on Reaction Time
can slow
the lock time considerably.
t
ACQ
-------------
8
K
ACQ
-------------
=
t
AL
V
f
RDV
-------------
4
K
TRK
-------------
=
t
Lock
t
ACQ
t
AL
+
=
F
Freescale Semiconductor, Inc.
n
.