參數(shù)資料
型號: MC68HC05P9ACDW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 4/158頁
文件大?。?/td> 3885K
代理商: MC68HC05P9ACDW
Timer
I/O Registers
Timer
Output Compare
Registers
When the value of the 16-bit counter matches the value in the read/write
output compare registers (OCRH and OCRL), the planned TCMP pin
action takes place. Writing to OCRH before writing to OCRL inhibits
timer compares until OCRL is written. Reading or writing to OCRL after
reading the timer status register clears the output compare flag (OCF).
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use the following procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading the timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code
register.
$0016
Bit 7
654321
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Unaffected by reset
$0017
Bit 7
654321
Bit 0
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Unaffected by reset
Figure 58. Output Compare Registers (OCRH and OCRL)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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