參數(shù)資料
型號: MC68HC05P9ACDW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 110/158頁
文件大?。?/td> 3885K
代理商: MC68HC05P9ACDW
Resets and Interrupts
Interrupts
Resets and Interrupts
1. V
DD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
2. The minimum t
ILIL should not be less than the number of interrupt service routine cycles
plus 19 t
CYC.
1. V
DD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
2. The minimum t
ILIL should not be less than the number of interrupt service routine cycles
plus 19 t
CYC.
Timer Interrupts
The capture/compare timer can generate the following interrupts:
Input capture interrupt
Output compare interrupt
Timer overflow interrupt
Setting the I bit in the condition code register disables timer interrupts.
Input Capture
Interrupt
An input capture interrupt request occurs if the input capture flag, ICF,
becomes set while the input capture interrupt enable bit, ICIE, is also set.
ICF is in the timer status register, and ICIE is in the timer control register.
Output Compare
Interrupt
An output compare interrupt request occurs if the output compare flag,
OCF, becomes set while the output compare interrupt enable bit, OCIE,
is also set. OCF is in the timer status register, and OCIE is in the timer
control register.
Table 12. External Interrupt Timing (V
DD = 5.0 Vdc)
(1)
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
t
ILIH
125
ns
Interrupt Pulse Period
t
ILIL
Note(2)
—t
CYC
Table 13. External Interrupt Timing (V
DD = 3.3 Vdc)
(1)
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
t
ILIH
250
ns
Interrupt Pulse Period
t
ILIL
Note(2)
—t
CYC
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