參數(shù)資料
型號: MC68HC05P9ACDW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 124/158頁
文件大?。?/td> 3885K
代理商: MC68HC05P9ACDW
Parallel I/O Ports
68
Parallel I/O Ports
Data Direction
Register A (DDRA)
Data direction register A determines whether each port A pin is an input
or an output.
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all eight port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 31 shows the I/O logic of port A.
Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 16 summarizes the operation
of the port A pins.
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
$0004
Bit 7
654321
Bit 0
Read:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Write:
Reset:
00000000
Figure 30. Data Direction Register A (DDRA)
Table 15. Port A Pin Operation
Data Direction Bit
I/O Pin Mode
Accesses to Data Bit
Read
Write
0
Input, Hi-Z(1)
Pin
Latch(2)
1
Output
Latch
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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