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參數(shù)資料
| 型號： | MC68HC05P9ACDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 52/90頁 |
| 文件大小： | 285K |
| 代理商： | MC68HC05P9ACDW |
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GENERAL RELEASE SPECIFICATION
MOTOROLA
ANALOG-TO-DIGITAL (A/D) CONVERTER
MC68HC05P9A
10-2
Rev. 2.0
10.2
A/D Status and Control Register (ADSCR)
The A/D status and control register contains a status ag and four writable control
bits.
CCF — Conversion Complete Flag
This read-only bit is automatically set when an analog-to-digital conversion is
complete, and a new result can be read from the A/D data register. CCF is
automatically cleared when a new conversion begins or when either the A/D
status and control register or the A/D data register is accessed. Writing to or
reading the A/D status and control register or the A/D data register starts a new
conversion sequence. Data from the previous conversion is overwritten
regardless of the state of the CCF bit. While CCF is a logical zero, the
requested A/D result is not yet available in the A/D data register.
ADRC — A/D RC Oscillator Control
When the RC oscillator is turned on, it requires a time (tADRC) to stabilize, and
results can be inaccurate during this time. If the internal clock rate is above 1
MHz, the ARDC bit should be cleared.
1 =
Internal RC oscillator drives A/D converter
0 =
Internal clock drives A/D converter
When the internal RC oscillator is being used as the A/D converter clock, two
limitations apply:
1. Because of the frequency tolerance of the RC oscillator and its
asynchronism with the internal clock, the conversion complete ag (CCF)
must be used to determine when a conversion sequence has been
completed.
2. The conversion process runs at the nominal 1.5 MHz rate, but the
conversion results must be transferred to the A/D data register
synchronously with the internal clock; therefore, the conversion process
is limited to a maximum of one channel every internal clock cycle.
ADON — A/D On
When the A/D is turned on, it requires a time (tADON) for the current sources to
stabilize. During this time, results can be inaccurate.
1 =
A/D converter enabled
0 =
A/D converter disabled
Bits 4–2 — Not Used
These bits are not used and read logical zero out of reset. Logical zeros must
be written to these bits when writing the A/D status and control register.
$001E
CCF
ADRC
ADON
0
CH1
CH0
RESET:
00000000
Figure 10-1. A/D Status and Control Register (ADSCR)
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05P9ACP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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| MC68HC05P9AMP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05P9AP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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