參數(shù)資料
型號(hào): MC68HC05P9ACDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁(yè)數(shù): 21/90頁(yè)
文件大小: 285K
代理商: MC68HC05P9ACDW
GENERAL RELEASE SPECIFICATION
MOTOROLA
INTERRUPTS
MC68HC05P9A
4-2
Rev. 2.0
4.1
Hardware Controlled Interrupt Sequence
The following three functions (RESET, STOP, and WAIT) are not interrupts in the
strictest sense. However, they are acted upon in a similar manner. Flowcharts for
hardware interrupts are shown in Figure 4-1, and for STOP and WAIT in Figure 6-
1. A discussion is provided below.
1.
RESET — A low input on the RESET input pin causes the program to
vector to its starting address, which is specied by the contents of
memory locations $1FFE and $1FFF. The I bit in the condition code
register also is set. Much of the MCU is congured to a known state
during this type of reset as described in SECTION 5 RESETS.
2.
STOP — The STOP instruction causes the oscillator to be turned off and
the processor to "sleep" until an external interrupt (IRQ) or reset
occurs.See 6.1.1 Stop Mode.
3.
WAIT or HALT — The WAIT or HALT instruction causes all processor
clocks to stop, but leaves the timer clock running. This rest state of the
processor can be cleared by reset, an external interrupt (IRQ), or timer
interrupt. These individual interrupts have no special wait vectors. See
6.1.2 Halt Mode.
Table 4-1. Vector Address for Interrupts and Reset
Register
Flag Name
Interrupts
CPU Interrupt
Vector Address
N/A
Reset
RESET
$1FFE-$1FFF
N/A
Software
SWI
$1FFC-$1FFD
N/A
External Interrupt
IRQ
$1FFA-$1FFB
TSR
ICF
Timer Input Capture
TIMER
$1FF8-$1FF9
TSR
OCF
Timer Output Capture
TIMER
$1FF8-$1FF9
TSR
TOF
Timer Overflow
TIMER
$1FF8-$1FF9
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