參數資料
型號: MC68HC05P9ACDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數: 41/90頁
文件大?。?/td> 285K
代理商: MC68HC05P9ACDW
GENERAL RELEASE SPECIFICATION
MOTOROLA
TIMER
MC68HC05P9A
8-2
Rev. 2.0
8.1
Counter
The key element in the programmable timer is a 16-bit, free-running counter or
counter register, preceded by a prescaler that divides the internal processor clock
by four. The prescaler gives the timer a resolution of 2.0 microseconds if the
internal bus clock is 2.0 MHz. The counter is incremented during the low portion
of the internal bus clock.
Software can read the counter at any time without
affecting its value.
The double-byte, free-running counter can be read from either of two locations,
$18-$19 (counter register) or $1A-$1B (counter alternate register). A read from
only the least signicant byte (LSB) of the free-running counter ($19, $1B)
receives the count value at the time of the read. If a read of the free-running
counter or counter alternate register rst addresses the most signicant byte
(MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value
remains xed after the rst MSB read, even if the user reads the MSB several
Figure 8-1. Timer Block Diagram
Input
Capture
Register
Clock
Internal Bus
Output
Compare
Register
High
Byte
Low
Byte
$16
$17
/4
Internal
Processor
16-Bit Free
Running
Counter
Alternate
Register
8-Bit
Buffer
High
Byte
Low
Byte
$1A
$1B
$18
$19
High
Byte
Low
Byte
$14
$15
Output
Compare
Circuit
Overflow
Detect
Circuit
Edge
Detect
Circuit
Timer
Status
Reg.
ICF OCF TOF $13
ICIE
IEDG OLVL
Output
Level
Reg.
RESET
Timer
Control
Reg.
$12
Output
Level
(TCMP)
Interrupt
Circuit
TOIE
OCIE
Edge
Input
(TCAP)
D
CLK
C
Q
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