參數資料
型號: MC68HC05J1AVDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝: SOIC-20
文件頁數: 85/126頁
文件大小: 1118K
代理商: MC68HC05J1AVDWR2
Parallel Input/Output (I/O)
Port A
MC68HC05J1A — Rev. 1.0
Technical Data
MOTOROLA
Parallel Input/Output (I/O)
61
7.4.2 Data Direction Register A
The contents of data direction register A (DDRA) determine whether
each port A pin is an input or an output. Writing a logic 1 to a DDRA bit
enables the output buffer for the associated port A pin; a logic 0 disables
the output buffer. A reset initializes all DDRA bits to 0, configuring all port
A pins as inputs.
DDRA7–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing DDRA bits from logic 0 to logic 1.
Address:
$0004
Bit 7
654321
Bit 0
Read:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Write:
Reset:
00000000
Figure 7-2. Data Direction Register A (DDRA)
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