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參數(shù)資料
| 型號： | MC68HC05J1AVDWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 62/126頁 |
| 文件大小： | 1118K |
| 代理商： | MC68HC05J1AVDWR2 |
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Technical Data
MC68HC05J1A — Rev. 1.0
40
Interrupts
MOTOROLA
Interrupts
An interrupt temporarily stops normal program execution to process a
particular event. An interrupt does not stop the execution of the
instruction in progress, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
central processor unit (CPU) registers on the stack and loads the
program counter with a user-defined vector address.
4.3.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.3.2 External Interrupts
These sources can generate external interrupts:
IRQ pin
PA3–PA0 pins (mask option)
Setting the I bit in the condition code register or clearing the IRQE bit in
the interrupt status and control register disables external interrupts.
4.3.2.1 IRQ Pin
An interrupt signal on the IRQ pin latches an external interrupt request.
When the CPU completes its current instruction, it tests the IRQ latch. If
the IRQ latch is set, the CPU then tests the I bit in the condition code
register and the IRQE bit in the interrupt status and control register. If the
I bit is clear and the IRQE bit is set, the CPU then begins the interrupt
sequence. The CPU clears the IRQ latch while it fetches the interrupt
vector, so that another external interrupt request can be latched during
the interrupt service routine. As soon as the I bit is cleared during the
return from interrupt, the CPU can recognize the new interrupt request.
Figure 4-1 shows the external interrupt logic.
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