參數(shù)資料
型號(hào): MC68HC05J1AVDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝: SOIC-20
文件頁數(shù): 80/126頁
文件大小: 1118K
代理商: MC68HC05J1AVDWR2
Low-Power Modes
Data-Retention Mode
MC68HC05J1A — Rev. 1.0
Technical Data
MOTOROLA
Low-Power Modes
57
6.6 Data-Retention Mode
In data-retention mode, the MCU retains random-access memory (RAM)
contents and CPU register contents at VDD voltages as low as 2.0 Vdc.
The data-retention feature allows the MCU to remain in a low
power-consumption state during which it retains data, but the CPU
cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic 0.
2. Lower the VDD voltage. The RESET pin must remain low
continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to logic 1.
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