參數(shù)資料
型號： MC68HC05F8FU
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PQFP64
封裝： PLASTIC, QFP-64
文件頁數(shù)： 77/126頁
文件大小： 1084K
代理商： MC68HC05F8FU
MOTOROLA
6-6
MC68HC05F8
TIMERS
6
TOIE - Timer Overow Interrupt Enable
1 (set)
–
Timer Overow interrupt enabled.
0 (clear) –
Timer Overow interrupt disabled.
IEDG - Input Edge
1 (set)
–
TCAP is positive-going edge sensitive.
0 (clear) –
TCAP is negative-going edge sensitive.
When IEDG is set, a positive-going edge on the TCAP pin will trigger a transfer of the free-running
counter value to the input capture registers. When clear, a negative-going edge triggers the
transfer.
OLVL - Output Level Voltage Latch
1 (set)
–
High output on TCMP pin if counter compare is true.
0 (clear) –
Low output on TCMP pin if counter compare is true.
There is a bit in the Event Enable register which may be used to disable and enable the
programmable timer.
TIMHA - Timer A Enable/Disable
1 (set)
–
Timer inhibit
0 (clear) –
Enable timer (default at reset)
6.1.5
Timer A Status Register (TSR)
The Timer Status register ($19) contains the status bits for the above three interrupt conditions -
ICF, OCF, TOF.
Accessing the timer status register satises the rst condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Event Enable Register
$16
TIMHA INTE1 INTE2
0
0000 0000
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on Reset
$19
ICF
OCF
TOF
0
uuu0 0000
TPG
52
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
相關(guān)PDF資料
PDF描述
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