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| 型號(hào)： | MC68HC05F8FU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 75/126頁(yè) |
| 文件大?。?/td> | 1084K |
| 代理商： | MC68HC05F8FU |
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MOTOROLA
6-4
MC68HC05F8
TIMERS
6
6.1.2
Output Compare Registers
–
Output Compare Register
High byte - $1C, Low byte - $1D
The 16-bit Output Compare register is made up of two 8-bit registers. This Output Compare
register is used for several purposes, such as indicating when a period of time has elapsed. All
bits are readable and writable and are not affected by the timer hardware or reset. If the compare
function is not needed, the Output Compare register can be used as storage locations.
The contents of the Output Compare register are continually compared with the contents of the
free-running counter and, if a match is found, the Output Compare Flag (OCF) in the Timer Status
register is set; and the output level (OLVL) bit is clocked to an Output Level register. The Output
Compare register value and the output level bit should be changed after each successful
comparison to establish a new elapsed time-out. An interrupt can also accompany a successful
output compare provided the interrupt enable bit (OCIE) is set. (The free-running counter is
updated every 4
÷R
TB internal bus clock cycles.)
After a processor write cycle to the output compare register containing the MSB ($1D), the output
compare function is inhibited until the LSB ($1D) is also written. The user must write both bytes
(locations) if the MSB is written rst. A write made only to the LSB ($1D) will not inhibit the
compare function. The processor can write to either byte of an output compare register without
affecting the other byte. The minimum time required to update the output compare registers is a
function of the program rather than the internal hardware. Because the output compare ag and
output compare register are not dened at power-on, and not affected by reset, care must be taken
when initializing output compare functions with software. The following procedure is
recommended:
1) write to Output Compare register high-byte to inhibit further compares;
2) read the Timer Status register to clear OCF;
3) write to Output Compare register low-byte to enable the output compare
function.
The output level (OLVL) bit is clocked to the output level register regardless of whether the output
compare ag (OCF) is set or clear.
6.1.3
Input Capture Registers
–
Input Capture Register
High byte - $1A, Low byte - $1B
‘Input Capture’ is a technique whereby an external signal (connected to TCAP pin) is used to
trigger a read of the free-running counter. In this way it is possible to relate the timing of an external
signal to the internal counter value, and hence to elapsed time.
The two 8-bit registers that make up the 16-bit Input Capture register, are read-only, and are used
to latch the value of the free-running counter after the corresponding input capture edge detector
senses a valid transition. The level transition that triggers the counter transfer is dened by the
TPG
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For More Information On This Product,
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For More Information On This Product,
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| MC68HC05J1 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
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