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參數(shù)資料
| 型號： | MC68HC05F8FU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 55/126頁 |
| 文件大?。?/td> | 1084K |
| 代理商： | MC68HC05F8FU |
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MOTOROLA
4-2
MC68HC05F8
RESETS
4
4.3
Illegal Address (ILADR) Reset
The MCU monitors all opcode fetches. If an illegal address space is accessed during an opcode
fetch, an internal reset is generated. Illegal address spaces consist of all unused locations within
the memory map and the I/O registers (see Figure 3-1). Because the internal reset signal is used,
the MCU comes out of an ILADR reset in the same operating mode it was in when the opcode was
fetched.
4.4
Computer Operating Properly (COP) Reset
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a
specic amount of time by a program reset sequence.
Note:
COP time-out is prevented by periodically writing a logic 1 to bit 7 of address $36.
If the watchdog timer is allowed to time-out, an internal reset is generated to reset the MCU.
Because the internal reset signal is used, the MCU comes out of a COP reset in the same
operating mode it was in when the COP time-out was generated.
The watchdog timer is initially disabled after a reset, it is enabled by writing a ‘1’ to bit 7 of address
$36. Once enabled, it cannot be disabled by software.
Refer to Section 6.3 for detailed description of the COP watchdog system.
Table 4-1 shows the internal circuit actions on reset, but not necessary in order of occurrence.
TPG
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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