參數(shù)資料
型號： MC68HC05F8B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PDIP56
封裝： PLASTIC, SDIP-56
文件頁數(shù)： 91/126頁
文件大?。?/td> 1084K
代理商： MC68HC05F8B
MC68HC05F8
MOTOROLA
7-3
SERIAL PERIPHERAL INTERFACE
7
7.2.2
Serial Data Output (SDO)
Data is transmitted in MSB rst format. The state of the SDO pin will always reect the value of
the rst bit receive on the previous transmission if there was one. Prior to enabling the SPI, PD5
can be initialized to determine the beginning state if a standard output since that pin is coupled to
the last stage of the serial shift register. On the first falling edge of SCK the rst data bit to be
shifted out is presented to the output pin.
7.2.3
Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SPI pin on the falling edge of SCK. Valid data must
be present at least 112ns before the rising edge of the clock and remain valid for 112ns after the
edge.
7.3
General Operation
A block diagram of the serial peripheral interface (SPI) is shown in Figure 7-3. In a master
conguration, the master start logic originates the system clock (SCK) based on the 447.5KHz (or
the E/4) clock. This clock is also used internally to control the state controller as well as the 8-bit
shift register. As a master device, data is parallel loaded into the 8-bit shift register (from the
internal bus) during a write cycle, data is applied serially from a slave device via SDI pin to the
8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred to the read
buffer and then is made available to the internal data bus a CPU read cycle.
In a slave conguration, the slave start logic receives a system clock input (from the master
device) at SCK pin. Thus, the slave is synchronized with the master. Data from the master is
received serially at the slave SDI and loads the 8-bit shift register. After the 8-bit shift register is
loaded, its data is parallel transferred to the read buffer and then is made available to the internal
data bus during a CPU read cycle. During a write cycle, data is parallel loaded into the 8-bit shift
register from the internal data bus and then shifted out serially to the SDO pin for application to
the master device.
One point to be noted, the SCK pin needs to be externally pulled high with 10K Ohms, in order to
bias the initial states at logic high.
7.4
SPI Registers
There are three registers associated with the serial parallel interface. They are the Serial
Peripheral Control register (SPCR, location $10), the Serial Peripheral Status register (SPSR,
location $11), and the Serial Peripheral Data I/O register (SPDR, location $12). Each register are
described below.
TPG
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For More Information On This Product,
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For More Information On This Product,
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