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參數(shù)資料
| 型號： | MC68HC05F8B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | PLASTIC, SDIP-56 |
| 文件頁數(shù)： | 46/126頁 |
| 文件大?。?/td> | 1084K |
| 代理商： | MC68HC05F8B |
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MOTOROLA
2-4
MC68HC05F8
PIN DESCRIPTIONS
2
2.3
Input/Output Programming
2.3.1
Parallel Ports
Port A, B, C, D, E, F and G may be programmed as an input or an output under software control.
The direction of the pins is determined by the state of corresponding bit in the port data direction
register (DDR). Each 8-bit port (except port G, where it has only 2 bits) has an associated 8-bit
data direction register. Any port A, B, C, D, E, F or G pin is congured as an output if its
corresponding DDR bit is set to a logic one. A pin is congured as an input if its corresponding
DDR bit is cleared to a logic zero. At power-on or reset, all DDRs are cleared, which congure all
port A, B, C, D, E, F and G pins as inputs. The data direction registers are capable of being written
to or read by the processor. Refer to Figure 2-3 and Table 2-1. During the programmed output
state, a read of the data register actually reads the value of the output data latch and not the I/O
pin.
2.3.2
Serial Port (SPI)
The serial peripheral interface (SPI) uses the port D pins for its function. The SPI function requires
three of the pins (PD5-PD7) for its serial data input (SDI), serial data output (SDO), and system
clock (SCK) respectively. See Section 7 for detailed description of SPI.
Table 2-1 I/O Pin Functions
R/W
DDR
I/O Pin Function
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
The I/O pin is in an output mode. The output data latch is read.
TPG
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For More Information On This Product,
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For More Information On This Product,
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